This role involves developing and verifying integrated Interface IP Subsystems. Additionally, you’d:
- Create design and verification specifications
- Architecture design, module design, test bench design, and test cases
- Define module interfaces and formats
- Evaluate and exercise various aspects of the development flow which may include such items as RTL development, functional simulation, constraint development, design for test, synthesis, timing exploration, power design, and verification coverage metrics
- Bachelor’s and/or master’s degree in electrical and/or Electronic Engineering, Computer Engineering or Computer Science
- Minimum 3 years of IP and/or ASIC Design/Verification/Applications experience required
- Hands-on experience in RTL coding, verification, synthesis, timing exploration, equivalence check, etc.
- Domain understanding of interface standards: PCIe, USB, Ethernet or DDR
- Good communication skills while interacting with internal teams and customers
- Experience in Design Compiler, Fusion Compiler, Spyglass or VC
- Experience in UVM methodology
- Experience in DesignWare Cores
- Experience in TCL, Perl, Python, or other shell scripting
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To view the job application please visit sjobs.brassring.com.