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Analog Design, Staff Engineer

Analog Design, Staff Engineer
by Admin on 05-10-2024 at 1:44 pm

Website Synopsys

Job Responsibilities:

  • Review 112G and 224G SerDes standards and architecture documents to develop analog sub-block specifications.
  • Identify and refine circuit implementations to achieve optimal power, area and performance targets.
  • Propose design and verification strategies that efficiently use simulator features to ensure highest quality design.
  • Oversee physical layout to minimize the effect of parasitics, device stress, and process variation.
  • Collaborate with digital RTL engineers on the development of calibration, adaptation and control algorithms for analog circuits.
  • Present simulation data for peer and customer review.
  • Mentor and Review the progress of junior engineers.
  • Document design features and test plans.
  • Consult on the electrical characterization of your circuit within the SerDes IP product.

Job Requirements:

  • PhD with 5+ years, or MSc with 8+ years of SerDes/High-Speed analog design experience.
  • In-depth familiarity with transistor level circuit design – sound CMOS design fundamentals.
  • Silicon-proven experience implementing circuits for the TX, RX and Clock paths within a SerDes
  • Detailed design experience with several of the following SerDes sub-circuits:
    receive equalizers, data samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase interpolator, delay-locked loop, phase-locked loop, bandgap reference, ADC, DAC
  • Experience optimizing FinFET CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects.
  • Awareness of ESD issues (i.e. circuit techniques, layout). and design for reliability (i.e. electro-migration, IR, aging, etc.).
  • Experience with EDA tools for schematic entry, physical layout, and design verification.
  • Knowledge of SPICE simulators and simulation methods.
  • Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture.
  • Experience with TCL, Perl, C, Python, MATLAB.
Apply for job

To view the job application please visit careers.synopsys.com.

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