Analog Design Engineer

Our Silicon Design & Verification business is all about building high-performance silicon chips—faster. We’re the world’s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance—eliminating months off their project schedules.
Analog Design Engineer
We are looking for Analog Design Engineer who will part of a SERDES high performance/high speed circuits development team.
Does this sound like a good role for you?
This role involves analyzing various mixed signal techniques for dynamic and static power reduction, performance enhancement and area reduction. You’d leverage your strong understanding of circuit simulation and circuit layout as well as knowledge of bipolar, CMOS, passive structure, and interconnect failure modes.
Main responsibilities

• Test bench and specification generation, analog design, documentation, layout coordination, verification
• The assurance of all the robustness and quality related aspects needed for high production yield and system level usability
• Silicon correlation analysis.

Key Qualifications

• Requires a degree in Electrical or Computer Engineering with specialization in Micro-electronics (or equivalent)
• Possesses relevant experience in deep submicron CMOS technologies.

• Exercises good judgment in selecting efficient/robust methods and techniques to design and validate electronic circuits.
• Good written and verbal communication in English
• Teamwork or Network relation experiences
• Problem-solving and organizational skills.

Preferred Experience

• 3+ years of relevant work experience in analog circuit design
• Background in mixed-signal block design, preferably related to high speed SERDES (Drivers, Receivers, Clocking, PLL, DLL, CDR)
• Knowledge of design for porting across multiple foundry nodes
• Familiar with custom analog layout techniques for signal integrity, high speed/performance and yield maximization, DFM mitigation, reliability and Latch-UP/ESD.