A&MS Circuit Design Engr, Sr II

Job Description and Requirements

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

A&MS Circuit Design Engineer, Senior II

In this role you would have the following responsibilities:

• Ensure analog sub-block performance adheres to SerDes standards and architecture document specifications.
• Identify and refine circuit implementations to achieve optimal power, area and performance targets.
• Propose design and verification strategies that efficiently use simulator features to ensure the highest quality design.
• Oversee physical layout to minimize the effect of parasitics, device stress and process variation.
• Work with digital RTL engineers on the verification of calibration, adaptation and control algorithms for analog circuits.
• Present simulation data for peer and customer review.
• Ownership of analog and mixed-signal building block that is integrated as part of a larger SerDes design.
• Document design features and test plans.
• Consult on the electrical characterization of your circuit within the SerDes IP product.

Key Qualifications

• Relevant experience or study background of SerDes/High-Speed analog design experience.
• Familiarity with the transistor-level circuit design of fundamental analog and mixed-signal building blocks- sound CMOS design fundamentals.
• Silicon-proven experience implementing circuits for analog and mixed-signal building blocks
• Design experience with some of the following SerDes sub-circuits:
  receive equalizers, data samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase interpolator, delay-locked loop, phase-locked loop, bandgap reference, ADC, DAC
• Experience optimizing CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects.
• Awareness of ESD issues (i.e. circuit techniques, layout). and design for reliability (i.e. electro-migration, IR, aging, etc.).
• Experience with EDA tools for schematic entry, physical layout, and design verification.
• Knowledge of SPICE simulators and simulation methods.
• Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture.
• Experience with TCL, Perl, C, Python, MATLAB.