WP_Term Object
(
    [term_id] => 51
    [name] => RISC-V
    [slug] => risc-v
    [term_group] => 0
    [term_taxonomy_id] => 51
    [taxonomy] => category
    [description] => 
    [parent] => 178
    [count] => 44
    [filter] => raw
    [cat_ID] => 51
    [category_count] => 44
    [category_description] => 
    [cat_name] => RISC-V
    [category_nicename] => risc-v
    [category_parent] => 178
    [is_post] => 1
)

SiFive Unveils E2 Core IP Series for Smallest, Lowest Power RISC-V Designs

SiFive Unveils E2 Core IP Series for Smallest, Lowest Power RISC-V Designs
by Camille Kokozaki on 07-06-2018 at 12:00 pm

Fully configurable with advanced feature sets allows for broad applications, including microcontrollers, IoT, wearables, and smart cards

The E20 and E21 add to the growing list of SiFive RISC-V cores addressing the embedded controller, IoT, wearables, smart toys. On June 25, DAC opening day, SiFive announced the availability of its E2 Core IP Series, configurable low-area, low-power microcontroller (MCU) cores designed for use in embedded devices. From their press release, the E2 Series extends SiFive’s product line with two new standard cores, the E21, which provides mainstream performance for MCUs, sensor fusion, minion cores and smart IoT markets; and the E20, the most power-efficient SiFive standard core designed for microcontrollers, IoT, analog mixed signal and finite state machine applications. Additionally, the company announced enhancements to its existing standard E3 and E5 Core IP Series.

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The SiFive E20 and E21 are designed for markets that require extremely low-cost, low-power computing, but can benefit from being fully integrated within the RISC-V software ecosystem. Fully compatible with the exact same software stack, tools, compilers and ecosystem vendors as other higher performance SiFive cores, the E2 Series enables these new markets to take advantage of the robust software ecosystem that has been exponentially growing since SiFive first introduced commercial RISC-V cores in 2016. Both cores are fully synthesizable and verified soft IP implementations that scale across multiple design nodes. The new product series provides a variety of new features, including a fully configurable memory map, multiple configurable ports, tightly integrated memory (TIM), fast IO access and a new CLIC interrupt controller for extremely fast interrupt response, hardware prioritization, and pre-emption.

Furthermore, SiFive gives designers the ability to configure a SiFive RISC-V Core Series to their specific application needs, with the ability to fine-tune performance, microarchitectural features, area density, memory subsystems and more within a given Core Series. Customers can either directly leverage the silicon-proven standard SiFive Core IP like the E21 or use it as a starting point for their own customizations.

Naveed Sherwani, SiFive’s CEO commented “I am happy to announce the availability of SiFive’s new E2 Series RISC-V Core IP. Its small area, low power, and low latency interrupt controller make it the obvious choice for many embedded applications. Like all SiFive IP, the E2 Series is fully customizable and can be configured to meet demanding high-performance applications as well as extremely low power and area sensitive applications. E2 Series evaluation RTL and FPGA images are available for free on our website.”

“SiFive’s Core IP is the foundation of the most widely deployed RISC-V cores in the world and represents the lowest risk and fastest path to customized RISC-V based SoCs,” said Yunsup Lee, co-founder, and CTO, SiFive. “Our Core IP Series takes advantage of the inherent scalability of RISC-V to provide a full set of customizable cores for any application – from tiny microcontrollers based on our new E2 Core IP Series to our previously announced, Linux-capable, multicore U Core IP Series.”

In addition to announcing the new E2 Core Series, SiFive also expanded its E3 and E5 Series to support coherent multicore configurations for high-performance embedded applications. In addition to multicore support, the E3 and E5 Series have a new enhanced multiplication unit which allows the E31 and E51 Standard Cores to achieve over 3 CoreMarks/MHz while still using open-source GCC compilers. The E3 and E5 Series are ideal for high-performance, real-time applications such as storage, industrial, modems, and networking.

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E Series: 32-bit and 64-bit Embedded Core IP
E5 Series – 64-bit Embedded Core IP
E5 Series embedded cores offer 64-bit performance at 32-bit price and area
E3 Series – 32-bit High Perf Core IP
High-performance 32-bit RISC-V embedded cores, the E3 Series is the most widely deployed RISC-V core in the world
E2 Series – 32-bit Lower Power Core IP *New*
SiFive’s smallest, lowest power, 32-bit core series. The E2 Series is optimized for deeply embedded, microcontroller applications

U Series: 64-bit Linux-Capable Core IP
U5 Series – 64-bit Applications Core IP
The world’s first RISC-V Linux capable core with high performance and optimized for maximum efficiency

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When I visited the SiFive booth of the RISC-V pavilion, Drew Barbier, their Sr Applications Engineer was highlighting the E2 series capabilities. He shared with me the following insight:

Some of the salient features of the E2 Series Memory Subsystem are:

  • The E2 core can be configured with 1 or 2 bus interfaces
  • The S-Bus is a highly optimized crossbar allowing fast access to the Tightly Integrated Memory banks (TIMs) and System Port
  • Optional parallel access support to 2 TIM banks with 2 bus interface configurations
  • Atomic instruction RISC-V support for single cycle Read-Modify-Write operation
  • E2 Core instruction and data accesses can target any Port or TIM

The Core Local Interrupt Controller (CLIC) provides:

  • A simplified interrupt scheme allowing low latency interrupt servicing, hardware prioritization, and pre-emption
  • Extreme low latency with support for Vectoring directly to ISR (6 cycles into first ISR instruction, 18 cycles to complete a simple ISR in E2 series pipeline)
  • Interrupt pre-emption capabilities with up to 16 nesting levels, and programmable priority levels within each level
  • An easy to use programmer model with GCC interrupt function attribute and no assembly, multiple software interrupts with programmable priority levels with drivers included in the SDK

For more information on SiFive’s RISC-V Core IP including full datasheets, specifications and app notes, visit www.sifive.com. More details on E2 can be found here. A SiFive E2 Series RISC-V Core IP Launch deck can be found here