Basilisk at Hot Chips 2025 Presented Ominous Challenge to IP/EDA Status Quo

At Hot Chips 2025, Philippe Sauter of ETH Zürich presented Basilisk, a project that may redefine what’s possible with open-source hardware. Basilisk is a 34 mm² RISC-V SoC fabricated at IHP Microelectronics on its open-source 130nm BiCMOS process in Germany. Basilisk, named after the Greco-Roman mythical creature known for its lethal gaze, runs full Linux and, more importantly, was produced entirely with open-source EDA tools. The achievement goes beyond a one-off demo. By proving that a Linux-capable SoC can be realized through fully open flows, ETH Zürich has pushed open hardware out of the realm of academic toys and into credible system platforms.

But the project also raises uncomfortable comparisons. Many large semiconductor companies sign on as RISC-V International members but stop short of actively supporting its summits or ecosystem growth. Why? Because the opportunity is also a threat. Open-source silicon promises sovereign compute and freedom from licensing models — but it undercuts the business of incumbent IP and EDA vendors.

U.S. semiconductor giants, in particular, have been slow to embrace this shift. The reasons are familiar: advanced-node tape-outs cost tens of millions, and proprietary vendors still provide the safety nets — warranties, sign-off certification, technical support — that open flows rarely offer. Risk avoidance has long been the rule, especially for companies that have amassed fortunes by comfortably making incremental changes. It’s as if everyone has forgotten the caution from Intel co-founder Andy Grove, who argued in his 1996 book Only the Paranoid Survive that even the most successful companies must anticipate disruption and act with urgency — or risk being left behind.

Sticking to the established order — and being left behind — is all too evident in today’s semiconductor industry. Andy Grove must be rolling in his grave as Intel — long the poster child for being “fat off the CPU monopoly” — missed the rise of GPUs as the engine of AI. ARM, meanwhile, seized the moment and established itself as the architecture of choice for DPUs, displacing Intel and AMD in datacenter networking almost overnight. It’s a stark reminder of how quickly incumbents can lose their grip when they lean too heavily on today’s profits.

The same dynamic is now unfolding with RISC-V and open-source EDA. In the U.S., most companies cling to familiar licensing models. Meanwhile, in China and Europe — where companies aren’t cushioned by legacy profits — risk-taking around sovereign IP and open flows is accelerating. The unsettling possibility for U.S. incumbents is that these challengers may build the ecosystems that eventually reshape the industry.

Sauter himself framed it clearly: “There’s strong momentum around open-source ISAs like RISC-V, but the toolchain remains a bottleneck. Our goal wasYosysHQ to show that fully open flows — Yosys, OpenROAD, and others — can tape out real silicon.” Yosys, an open-source framework for digital logic synthesis, created by Claire Xenia Wolf, CTO of , transforms high-level hardware descriptions (typically in Verilog) into gate-level netlists, making it a cornerstone of open-source silicon design.

OpenROAD (Open Real-time Automated Design) is a pioneering open-source project aimed at democratizing digital chip design by making the entire RTL-to-GDSII flow accessible, automated, and free to use. OpenROAD is supported by FOSSi (Free and Open-Source Silicon Initiative), Foundation and featured in European open EDA roadmaps.

And Basilisk is no toy core. It integrates a single-issue, in-order RV64GC CPU core (CVA6 from the OpenHW Group) with MMU, instruction/data caches, and a HyperRAM controller, supported by a Linux software stack. CVA6 is in the same application-class category as SiFive’s P800 and Andes’ AX46, offering Linux-capable execution and full ISA support. While CVA6 prioritizes open-source transparency and in-order simplicity, P800 and AX46 push into high-performance, out-of-order territory for commercial deployments.  ETH Zürich and IHP chose the mature 130nm BiCMOS process not for bleeding-edge performance but to prove open flows could converge on a working, Linux-capable chip at manageable cost and risk.

A 48×48 double-precision GEMM workload was used to evaluate ten packaged Basilisk chips, with measurements taken at room temperature. At a nominal voltage of 1.2 V, the chips operated at 64 MHz, consistent with final timing analysis from OpenROAD. Under maximum voltage conditions (1.64 V), peak frequency reached 102 MHz. Notably, the highest energy efficiency — 18.9 MFLOP/s/W — was achieved at a reduced core voltage of 0.88 V, demonstrating that open-source designs can exploit a voltage-scalable performance envelope.

The team reports tangible gains over baseline open flows as shown in the figure. These results, achieved through extensive synthesis, placement, and routing optimizations, demonstrate that open EDA can approach industrial standards with the right engineering effort. The next project, targeting GlobalFoundries’ 22FDX, will scale dramatically — with 10–20× more gates/transistors, compute clusters, and ML-oriented accelerators targeting >1 TFLOP/s performance. Success there could elevate open flows from academic milestone to industrial contender.

Sauter also highlighted a nuance often lost in debates: open-source EDA tools are not merely competition to incumbents — they are also an opportunity. Universities worldwide can now train engineers in how these flows work, seeding a generation of graduates who are better prepared to collaborate with or even improve commercial tools. EDA vendors themselves could benefit by leveraging open frameworks for AI-guided tool flows, an area of intense industry research. Open tools may expand, not shrink, the talent and innovation pipeline.

Basilisk is produced on IHP’s (German research fab) 130nm BiCMOS process, which has an open-source process-design-kit. Basilisk is not a solo effort. It is funded and enabled by the PULP-Platform group led by Prof. Luca Benini, IHP, and the SwissChips initiative — the Swiss government’s national chip program. This backing underscore a broader shift: governments and research institutions are investing in open silicon as a matter of strategic sovereignty.

Hot Chips 2025 was dominated by posters on AI accelerators and memory-centric architectures. Basilisk stood out because it wasn’t about another specialized accelerator — it was about the foundation of open innovation itself. For startups and labs priced out of proprietary flows, Basilisk is more than a chip. It’s a signal: the walls around silicon design are beginning to come down.