Arteris at the 2024 Design Automation Conference

Arteris, a leading provider of system IP, will exhibit at DAC 2024, June 23-27, booth #1506. The company will demonstrate its latest technology including network-on-chip interconnect IP and SoC integration automation solutions. The products highlighted include CSRCompiler, Ncore Cache Coherent NoC IP and FlexNoC 5 interconnect IP.

Arteris recently released enhancements to CSRCompiler, a vital software solution in their system-on-chip (SoC) integration automation strategy that also includes Magillem Registers and Magillem Connectivity ( check out the recent SemiWiki blog on the Magillem suite of products here). CSRCompiler reduces manual errors and enhances productivity by streamlining the generation of hardware/software interface (HSI) outputs. CSRCompiler supports rapid, iterative designs and ensures consistency across multiple teams, automating the generation of HSI requirements from high-quality RTL and software to design verification and documentation. This software solution utilizes SystemRDL 2.0, ensuring consistency across various views and organizations without time-consuming manual scripting and editing.

CSRCompiler’s HSI database is essential for architects, RTL designers, verification engineers, software developers, and technical writers, offering centralized and customized HSI information. It compiles thousands of registers within seconds and millions within minutes. The software solution’s adaptable architecture supports various input formats into a single source, ensuring efficient production of all required formats and helping avoid errors in address map deployment. This comprehensive approach reduces the HSI development process by up to one-third.

Recently released, the updated Ncore cache coherent network-on-chip (NoC) IP ensures low latency integration of hardware accelerators into a coherent domain, delivering the speed and efficiency required for cutting-edge applications in complex SoC designs. By using Ncore, SoC design teams can save more than 50 years of engineering effort per project compared to interconnect solutions that are manually generated.

Ncore supports multiple processor IPs, including the recently announced Armv9 Cortex processor and RISC-V. Its multi-protocol support allows seamless integration of IPs connected to the same NoC fabric. It offers flexibility with CHI-E, CHI-B, ACE fully coherent agent interfaces, ACE-Lite IO-coherent interfaces, and AXI for non-coherent sub-systems.

Ncore’s configurability and scalability allow SoC designers to meet specific PPA requirements with flexible fine-tuning of the NoC architecture. It is also certified for use in ISO 26262-compliant from ASIL B to ASIL D for automotive and other mission-critical systems.

Unveiled last year, FlexNoC 5, Arteris’ latest non-coherent NoC interconnect IP, is a game-changer for SoC architecture teams. Its physical awareness eliminates the need for lengthy NoC placement and route iterations, significantly reducing development time. This technology enables 5X faster physical convergence over manual refinements, leading to improved performance, lower power consumption, and reduced die size, all of which are crucial for efficient SoC design. The interconnect enhances compatibility with other SoC IP blocks through the Arteris Magillem connectivity flow.

FlexNoC 5 supports several topologies, as well as Arm AMBA 5 protocols and IEEE 1685 IP-XACT. Additionally, it offers a Functional Safety (FuSa) option compliant with ISO 26262 standards up to ASIL D, enhancing its suitability for safety-critical applications.

Arteris invites you to visit booth #1506 at DAC 2024, to meet their experts and explore how these technologies can benefit your SoC designs. You can also catch the following DAC sessions featuring Arteris:

NoC NoC – Who’s There?
Monday, June 24 from 3:30-5:00 pm
Location: 2012, 2nd Floor

A Single Source Unified Approach to CSR Register Development Poster Presentation
Monday, June 24 from 5:00-6:00 pm
Location: Level 2 Exhibit Hall

Accelerating Timing Closure for Network on Chips (NoCs) using Physical Awareness
Wednesday, June 26 from 1:30-3:00 pm
Location: 2012, 2nd Floor

If you can’t make it DAC, Arteris invites you to learn more at www.arteris.com.

Also Read:

Arteris is Solving SoC Integration Challenges

Arteris Frames Network-On-Chip Topologies in the Car

Arteris is Unleashing Innovation by Breaking Down the Memory Wall