PCI Express in Depth

This is another post that was requested by a user, and as always i’ll do my best to put in a few articles the basic information that you’ll need to understand how it works at depth level.

PCI Express (or PCIe) is a high-speed serial computer expansion bus designed to replace the older PCI, PCI-X and AGP standards.

The first principle you need understand is the LANES, a lane is composed of two differential signaling pairs, with one pair for receiving data and the other for transmitting. Thus, each lane is composed of four wires or signal traces. Conceptually, each lane is used as a full-duplex byte stream, transporting data packets in eight-bit “byte” format simultaneously in both directions between endpoints of a link.

The connection between two PCIe devices is referred to as a link, physical PCIe links may contain from 1 to 16 lanes, more precisely 1, 4, 8 or 16 lanes. Lane counts are written with an “x” prefix (for example, “x8” represents an eight-lane card or slot), with x16 being the largest size in common use. Lane sizes are also referred to via the terms “width” or “by” e.g., an eight-lane slot could be referred to as a “by 8” or as “8 lanes wide.”

Others concepts include:

• PCIe elements types:

1. Root Complex – Is the head or root of the connection.
2. PCI Express-PCI bridge – As the name says has one PCI Express port and one or multiple PCI/PCI-X bus interfaces.
3. Endpoint – is a device that can request/complete PCI Express transactions for itself
4. Switch – are used to fan out a PCI Express hierarchy.

• PCIe Transactions Types:

1. Memory Transaction – Transactions targeting the memory space transfer data to or from a memory-mapped location
2. I/O Transactions – Transactions targeting the I/O space transfer data to or from an I/O-mapped location
3. Configuration Transactions – Transactions targeting the configuration space are used for device configuration and setup
4. Message Transactions – PCI Express adds a new transaction type to communicate a variety of miscellaneous messages between PCI Express devices

The architecture is show in the figure below:

The next three articles will be about theses three layers: Physical Layer, Data Link Layer and Transaction Layer.

As always, leave a comment, just tell me which protocol or standard you want to know more about it.