I suppose it is possible that Intel has turned another leaf and that 18A is on-track, yielding well, and performing well fulfilling the 5N4Y plan in stellar fashion. I just get stuck recalling the history of 14+++++ and 10+++++. Fool me once, shame on you, fool me 8 times? Ya get what I am saying
.
I think that is valid. However, to be fair, the situation is far different from it was. Back then, Intel's TD org was running on an insufficient R&D budget to keep pace with a TSMC or a Samsung (although Samsung is hard to say since we don't know what the TD wafer split is between memory and logic at Samsung). Additionally, after intel announced that 6-12 month delay to their "7nm" Intel has largely delivered what they said they would when they said they would. 10nm Super Fin was delivered on time and was a strong enhancement on top of then now functional 10nm. Intel 7 also was on time and with some spare gas in the tank to allow for a meaningful refresh with 13th gen. Intel 4 was on time, exceeded the PPA targets intel suggested, was much more cost competitive, and had the high early yields that Intel was historically known for. Intel said intel 3 was ahead of schedule and enabled Xeon 6 E-core to start shipping final product to customers earlier than what Intel originally was guiding (Q1'24 vs Q2'24). As I had previously pointed out, Intel 3 was also better than intel originally guided, and is evidently yielding pretty well since Intel has launched big die Xeons on it/it is basically intel 4 with extra performance optimizations.
FWIW, it isn't really that long ago that TSMC had a fairly spotty execution record. 130nm had issues with the interconnect dielectric, TSMC 65nm was late so UMC was able to get there first (the first and only time UMC beat TSMC to a given node). 45nm got canceled because it was late to yield, and 40nm had poor early yields and a large PDK shake up that threw off NVIDIA. 32nm-HP (HKMG), 32nm-LP (poly-Si gate), and 28nm-LP (poly-Si) were all canceled. From what I can gather it seems like early 28nm-HP (HKMG) early ramp didn't seem to live up to the standard TSMC normally sets (but given how horrible the gate first processes turned out, TSMC did a pretty very good job here when we grade them on a curve with the other foundries). 20nm had an ill-conceived process definition and poor value prop, so few people used it, and none of those customers used it long term. 16FF had a slow ramp, so Apple had to dual source with the faster ramping Samsung. 10FF had low early yield and also became an orphan process with fab space being converted to N7. In recent times the only public slip-up I can think of was N3 being a year late and required a redesigned FEOL/MEOL process (N3E) that isn't seamless for designers. Beyond that N7 and N5 were REALLY well executed, and 28nm HKMG/16FF were solidly executed. N3E is also superb because TSMC was juggling the N3 issues with Apple and Intel breathing down their necks while also spinning up a new from the ground up process flow.
I say all that to say this. Teams evolve. TSMC has leveled up their game a lot over the past 10–15 years. I have little faith that 2000s TSMC would have been able to navigate the debacle that their SAC/SAGE process caused them anywhere near as well as 2020s TSMC did. Recent history seems to indicate that the woes of intel's process development department are behind them. If TSMC leveled up beyond what they were ever capable of in the past, I don't see why Intel can't level up to what they used to consistently demonstrate every time for the better part of two decades. IMO if 18A continues on a strong yield ramp, then I think you can take an intel process roadmap to the bank, the same way one would implicitly trust in a recent TSMC roadmap.
I also am basing my skepticism on my engineering background and decades of large, complex programs.
When you are aggressive in your requirements, the chance of failure increases exponentially with the degree of aggression. It is very common for original requirements to be relaxed as you approach production in order to reduce risk (in fact, I can't recall a single time this did not happen).
Agreed. That is the beauty in intel doing with 18A, no? Both Ann K at interviews and some SPIE papers talked about how now Intel uses quick turn monitors and develops the different process segments in a modular manner and with parallel schemes to make debugging issues easier and enabling fallback options. They also had a stepwise adoption for BSPDN with a risk reduction process composed of an intel 4 FEOL mated to the 20A BEOL process to derisk powerVIA which they got to have yields trailing intel 4 by a mere 2Q offset. Also using that opportunity to figure out how to do assembly test, and best optimize chip design around in the new BSPDN environment. Then there was also a small die Arrow lake CPU "tile" to further derisk things. Of course that never came to pass due to cost reduction reasons, but Intel claims 18A is in a good enough state that 20A Arrow lake doesn't really serve its purpose of derisking 18A anymore.
Historically, Intel put a focus on only doing one main new thing for a process node, plus maybe one smaller thing to reduce risk. It is good to see that Intel has gone back to what worked so well in the past, and what worked so well for TSMC in that multipatterning/early EUV era.
Also, Samsung has had serious issues yielding good GAA product. The GAA process appears to be much more involved than FinFET is with more steps, and more complex steps needed to achieve the process.
You would be correct here. GAA requires many novel process modules and also breaks things that work in finFET. The three examples I see the most in lititure are lower mobility from the crystal orintation that the majority of the charge carieers move through changing, having enough space for your Gox and metal fill for the replacement metal gate process, and faults in your EPI S/D as the EPI growth fronts from each of the nanosheets collide to create strain relaxing faults.
(aside) While I am at it, talking about processes in terms of the label seems quite outdated. Are there ANY traces in Intel's 18A that are only 18A wide?
If by traces you mean metal lines, then Intel's papers would indicate not. Various FEOL critical dimensions of in production finFET and GAA processes have single digit nanometer in size. But things like gate length and minimum feature size are far larger than 2nm large. But that is a conversation that has been done to death, and it hasn't been true for anyone's process for decades at this point.
Their libraries are all totally non-backwards compatible to my understanding so there really isn't much of a backup plan if things don't go well.
That wasn't the case on intel 4 and 3, so I don't know why it would be assumed that 18A wouldn't offer a superset of 20A. Also, I don't really see your point here. If for example N2 is late, there isn't exactly a backup plan either. You can't just wave a magic wand and have your N2 chip become an N3P chip in under a year.
As an example, Intel had a less-than-stellar introduction of desktop Arrow Lake. A day or two after reviews, Intel announced it would be releasing a major microcode update that would improve performance noticeably ...... which we now have no trace of, and rumors and leaks don't look that favorable for. In other words, it seems like an empty promise again.
Intel products once again falling on their face is hardly intel foundry's fault. If anything, it is evidence to stop assuming that intel foundry is at fault for every little issue at the wider intel if products made at TSMC can disappoint just as poorly as those made at Intel.
Honest question - what WAS the last desktop focused architecture?
Meteor Lake and Arrow lake platforms. The designs are suboptimal for mobile in the name of desktop scalability. At a recent investor meeting, they even mentioned how the current products and many of the immediate future products were designed with the intent of maximum performance at all costs, and now that intel products has to run their business as if they were a fabless firm without the crutch of margin stacking they are designing products in a more deliberate manner. For mobile, a design would ideally be monolithic for lowest power consumption. MTL/ARL are also expensive to produce (large die sizes and advanced packaging). For desktop parts that frequently carry higher margins, not a huge problem. In Intel's bread and butter mobile segment, very much a problem. If anyone doesn't want to believe me that these are platforms compromised by not being mobile focused, I point to Intel making even more expensive lunar lake their main premium mobile offering because MTL/ARL are not desirable laptop chips at your highest volume 15W and below or even 28W and below segments.
(Also not popular here but I think Arrow Lake would probably clock higher on Intel 7 Ultra than it's current TSMC N3B node - so I think it's even got a slight disadvantage there on the desktop too).
If we are comparing anything to Intel 7 ultra it's difficult to match the clock speed it offers
You would be wrong on this count. An Intel 7 version would clock far slower. Refer to this post for why it is physically impossible for an Intel 7 version to be better and how design has a larger impact on Fmax:
I'm not being snarky, but you are obfuscating. Nonsense. Innovators Dilemma may easily apply, since design can be a function of the designers environment, and an environment with or without internal fabrication constraints, are clearly different. Here you go again. How are design...
semiwiki.com
