The fact that the source power for EUV lithography (EUVL) is still a sore spot in the drive to roll out the advanced patterning of ICs for high-volume manufacturing (HVM) is nothing new to industry experts. What might offer a way to ease the conundrum comes by way of a SEMATECH collaboration with Cornell University in the area of novel EUV imaging materials. Brewer Science believes that the industry has made progress evaluating various EUV imaging materials (e.g., inorganic resists), and in general there is some good news on the topic of EUV masks. Another infrastructure gain will surely come from the initiative just launched by SEMATECH to address the need for high-throughput inspection.
EUV Imaging Materials
SEMATECH has active programs looking at novel EUV imaging materials. The research consortium recognizes that while conventional photoresists have been making incremental improvements, the results are not closing the gap. Therefore, focus has been placed on novel imaging chemistries. Mike Lercel, senior director of Technology at SEMATECH, singled out work being done in conjunction with Christopher Ober’s Polymer Research Materials group at Cornell University on metal oxide nanoparticle-enabled EUV resists that could mitigate the need for a 250W source power requirement with very high-sensitivity resists. “They [Ober‘s group] use an imaging mechanism that appears to be dramatically different from
conventional photoresists,” said Lercel.
(Figure 1 shows results of work done by SEMATECH in partnership with Cornell).
“They reported some resists that had exposure doses under 2mJ/cm[SUP]2[/SUP].” He added that most of the other materials being reported are in the range of 20, while the scanner target is 15. “So I think that two is probably a bit optimistic, but if you really could get a factor of 10, your 250W source power requirement drops down to something like 25W. That would be a huge breakthrough, though more work is required, such as imaging quality (e.g., line width roughness, or LWR, needs improvement),” added Lercel, who will present at the “Breakthrough High-Volume Manufacturing (HVM) Innovations: New Paradigms for the Road Ahead” session at SEMICON West 2014 on July 10.
Douglas Guerrero, senior technologist at Brewer Science, told SEMI that the main issues for EUV resists are line collapse for sub-20nm patterning and the simultaneous improvement in LWR, sensitivity, and resolution. “Some resists that show good LWR values have high dose requirements,” noted Guerrero, who will present at the SEMICON West 2014 session on “Readiness of Advanced Lithography Technologies for HVM” on July 9. “In my opinion, the dose requirement of <15mJ/cm[SUP]2[/SUP] is a bit artificial because it only addresses the state of the illumination sources in EUV exposure tools.” Guerrero believes that a dose in the 20-30mJ range is a more realistic target that will allow for reduction of LWR. “As we look toward the future, resists will continue to shrink, and that will also cause high LWR problems, therefore, the future of chemically amplified resists for single digit nodes does not look very promising. Even with post-lithography processes to reduce LWR, the problems with pattern collapse and resolution need to be addressed.” He further explained that some researchers are shifting R&D efforts from traditional resists to inorganic resists. “These resists can be very thin and have promising properties, except for the extremely high dose required (i.e., >50mJ range).”
As the industry continues its scaling efforts down to 5nm, Guerrero explained that in order to maintain a 2:1 aspect ratio (height to width), which minimizes line collapse, resists will need to be thinner. “The less resist that is available, however, the less contrast and etch budget remain, and the more difficult it is to perform metrology (e.g., for CD and defectivity),” said Guerrero. “A thinner resist leads to higher LWR. This effect has been correlated to increased shot noise, random resist deprotection, and lowering of the coefficient of thermal expansion of the resist.” The technical challenges then are to redesign materials and the imaging stack. “Directed Self Assembly (DSA) is a complementary technology with the promise of addressing these issues, but the materials and processes need maturity.” Guerrero also noted that DSA’s chief hurdle is high defectivity and access to simplified flows.
SEMATECH also has an active program to address what is generally acknowledged to be the #2 challenge with EUVL: mask defects. The consortium has presented data showing a 40% reduction in large killer defects, with an average of five large defects per mask blank across the runs (a mask blank is six inches square). “People have been driving for zero defects for a very long time,” said Lercel. “But the reality is, you need to get to zero for the killer (or major) defects because you can’t compensate for them.” The expectation then, is that some compensation can be made for the smaller defects.
Metrology and Inspection Readiness for EUVL
Defect inspection is a necessity regardless of which lithography technology is used, and SEMATECH is working on ways to ensure yield and cost-effective solutions. Lercel told SEMI that defect inspection has not kept pace with the industry’s needs. The two techniques in use each are problematic. High-throughput optical inspection is challenged by issues like trying to find 20nm defects in a 20nm line, while the other technique (e.g., e-beam inspection) is much slower and typically used for early process development work — not useful when looking for a small number of defects over large areas. The gap between these two inspection techniques is increasing, noted Lercel, who said that the real question is how the industry reaches a high-throughput capability that allows very high device yields as it scales down to sub-10nm nodes. “Optical inspection needs to be at a lot higher sensitivity, or e-beam inspection needs to be a lot faster.” SEMATECH just launched a project to address the need for high-throughput inspection, but additional details are not yet available.
The Future of EUVL
Clearly, much work has been done and progress is continuing to bring EUVL to fruition as a solution for advanced lithography in an HVM environment. EUVL could very well present one of the most confounding dilemmas yet. The industry, however, has always been pragmatic when it comes to the technologies it chooses.
Guerrero views the situation in two different lights: usefulness and timing. “There is no question that EUVL is useful, however, it needs a minimum throughput of about 75 wafers/hour to be economically feasible for HVM.” He also observes that EUVL can provide a platform onto which the industry can do all future patterning — a situation he likens to what has happened with immersion lithography. “Meaning, we can use the EUVL platform and apply other extension and patterning tricks to last us until the end of device shrinking as we know it today.” He also notes that EUVL single-patterning would bring very significant cost reduction benefits by decreasing the number of masks required vs. multiple patterning. “It will also allow for single patterning of complex designs that are not possible today. The technology has proven and future benefits.”
Not to overstate the obvious, but Guerrero notes that EUVL is clearly too late for HVM for this year or next year. “The loss in confidence with EUVL is that it has always been two years away from being a reality for HVM,” Guerrero told SEMI. “If the source issues are resolved in the next 18-24 months, then it can still be used. However, it is not going to be a technology for the masses as we have seen in the past with other technologies.” Guerrero allows that the cost of EUVL will be high and only a few will adopt it — he speculates that the number of adoptees may only be five. Also on his mind is what happened with 157nm lithography. For example, if only two of the major players drop out, then EUVL might disappear (as did 157nm). “I think this is what people are waiting to hear, who is going to drop out first before the whole thing goes away. Intel? TSMC? Samsung? With only one tool and source supplier left, the economics of having only three customers might not work for it to survive. So the answer is not crystal clear. It all depends on how much patience the stakeholders have and willingness to put resources into it.”
Hear from companies like Applied Materials, ASML, Brewer Science, Canon Nanotechnologies, CEA-Leti, CNSE, Intel, Mentor Graphics, Nikon, SEMATECH, SUNY CNSE, UMC and many more at the Semiconductor Technology Symposium sessions at SEMICON West 2014 in San Francisco, Calif. Dr. Burn Lin, VP of R&D at TSMC, will moderate the STS Lithography session.
Other upcoming SEMI expositions include: SEMICON Taiwan 2014 (September 3-5), SEMICON Europa 2014 (October 7-9) and SEMICON Japan 2014 (December 3-5).
By Debra Vogler, SEMI
June 30, 2014
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EUV Imaging Materials
SEMATECH has active programs looking at novel EUV imaging materials. The research consortium recognizes that while conventional photoresists have been making incremental improvements, the results are not closing the gap. Therefore, focus has been placed on novel imaging chemistries. Mike Lercel, senior director of Technology at SEMATECH, singled out work being done in conjunction with Christopher Ober’s Polymer Research Materials group at Cornell University on metal oxide nanoparticle-enabled EUV resists that could mitigate the need for a 250W source power requirement with very high-sensitivity resists. “They [Ober‘s group] use an imaging mechanism that appears to be dramatically different from
conventional photoresists,” said Lercel.
Figure 1 EUV lithography demonstrating 20nm and 30nm line-space patterns on ZrO2-DMA and HfO2-DMA resist films with very high EUV sensitivity.SOURCE: SEMATECH/Cornell University
(Figure 1 shows results of work done by SEMATECH in partnership with Cornell).
“They reported some resists that had exposure doses under 2mJ/cm[SUP]2[/SUP].” He added that most of the other materials being reported are in the range of 20, while the scanner target is 15. “So I think that two is probably a bit optimistic, but if you really could get a factor of 10, your 250W source power requirement drops down to something like 25W. That would be a huge breakthrough, though more work is required, such as imaging quality (e.g., line width roughness, or LWR, needs improvement),” added Lercel, who will present at the “Breakthrough High-Volume Manufacturing (HVM) Innovations: New Paradigms for the Road Ahead” session at SEMICON West 2014 on July 10.
Douglas Guerrero, senior technologist at Brewer Science, told SEMI that the main issues for EUV resists are line collapse for sub-20nm patterning and the simultaneous improvement in LWR, sensitivity, and resolution. “Some resists that show good LWR values have high dose requirements,” noted Guerrero, who will present at the SEMICON West 2014 session on “Readiness of Advanced Lithography Technologies for HVM” on July 9. “In my opinion, the dose requirement of <15mJ/cm[SUP]2[/SUP] is a bit artificial because it only addresses the state of the illumination sources in EUV exposure tools.” Guerrero believes that a dose in the 20-30mJ range is a more realistic target that will allow for reduction of LWR. “As we look toward the future, resists will continue to shrink, and that will also cause high LWR problems, therefore, the future of chemically amplified resists for single digit nodes does not look very promising. Even with post-lithography processes to reduce LWR, the problems with pattern collapse and resolution need to be addressed.” He further explained that some researchers are shifting R&D efforts from traditional resists to inorganic resists. “These resists can be very thin and have promising properties, except for the extremely high dose required (i.e., >50mJ range).”
Figure 2. Example of inorganic resist performance showing low LWR and resolution.
SOURCE: Inpria.
SOURCE: Inpria.
As the industry continues its scaling efforts down to 5nm, Guerrero explained that in order to maintain a 2:1 aspect ratio (height to width), which minimizes line collapse, resists will need to be thinner. “The less resist that is available, however, the less contrast and etch budget remain, and the more difficult it is to perform metrology (e.g., for CD and defectivity),” said Guerrero. “A thinner resist leads to higher LWR. This effect has been correlated to increased shot noise, random resist deprotection, and lowering of the coefficient of thermal expansion of the resist.” The technical challenges then are to redesign materials and the imaging stack. “Directed Self Assembly (DSA) is a complementary technology with the promise of addressing these issues, but the materials and processes need maturity.” Guerrero also noted that DSA’s chief hurdle is high defectivity and access to simplified flows.
Metrology and Inspection Readiness for EUVL
Defect inspection is a necessity regardless of which lithography technology is used, and SEMATECH is working on ways to ensure yield and cost-effective solutions. Lercel told SEMI that defect inspection has not kept pace with the industry’s needs. The two techniques in use each are problematic. High-throughput optical inspection is challenged by issues like trying to find 20nm defects in a 20nm line, while the other technique (e.g., e-beam inspection) is much slower and typically used for early process development work — not useful when looking for a small number of defects over large areas. The gap between these two inspection techniques is increasing, noted Lercel, who said that the real question is how the industry reaches a high-throughput capability that allows very high device yields as it scales down to sub-10nm nodes. “Optical inspection needs to be at a lot higher sensitivity, or e-beam inspection needs to be a lot faster.” SEMATECH just launched a project to address the need for high-throughput inspection, but additional details are not yet available.
The Future of EUVL
Clearly, much work has been done and progress is continuing to bring EUVL to fruition as a solution for advanced lithography in an HVM environment. EUVL could very well present one of the most confounding dilemmas yet. The industry, however, has always been pragmatic when it comes to the technologies it chooses.
Guerrero views the situation in two different lights: usefulness and timing. “There is no question that EUVL is useful, however, it needs a minimum throughput of about 75 wafers/hour to be economically feasible for HVM.” He also observes that EUVL can provide a platform onto which the industry can do all future patterning — a situation he likens to what has happened with immersion lithography. “Meaning, we can use the EUVL platform and apply other extension and patterning tricks to last us until the end of device shrinking as we know it today.” He also notes that EUVL single-patterning would bring very significant cost reduction benefits by decreasing the number of masks required vs. multiple patterning. “It will also allow for single patterning of complex designs that are not possible today. The technology has proven and future benefits.”
Not to overstate the obvious, but Guerrero notes that EUVL is clearly too late for HVM for this year or next year. “The loss in confidence with EUVL is that it has always been two years away from being a reality for HVM,” Guerrero told SEMI. “If the source issues are resolved in the next 18-24 months, then it can still be used. However, it is not going to be a technology for the masses as we have seen in the past with other technologies.” Guerrero allows that the cost of EUVL will be high and only a few will adopt it — he speculates that the number of adoptees may only be five. Also on his mind is what happened with 157nm lithography. For example, if only two of the major players drop out, then EUVL might disappear (as did 157nm). “I think this is what people are waiting to hear, who is going to drop out first before the whole thing goes away. Intel? TSMC? Samsung? With only one tool and source supplier left, the economics of having only three customers might not work for it to survive. So the answer is not crystal clear. It all depends on how much patience the stakeholders have and willingness to put resources into it.”
Hear from companies like Applied Materials, ASML, Brewer Science, Canon Nanotechnologies, CEA-Leti, CNSE, Intel, Mentor Graphics, Nikon, SEMATECH, SUNY CNSE, UMC and many more at the Semiconductor Technology Symposium sessions at SEMICON West 2014 in San Francisco, Calif. Dr. Burn Lin, VP of R&D at TSMC, will moderate the STS Lithography session.
Other upcoming SEMI expositions include: SEMICON Taiwan 2014 (September 3-5), SEMICON Europa 2014 (October 7-9) and SEMICON Japan 2014 (December 3-5).
By Debra Vogler, SEMI
June 30, 2014
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