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The problem with SAC is etch. If you do your gate cut after RMG your etch needs to eat W but the contacts are also W. And the whole reason TSMC went with SAC was it was getting to hard to place the contacts lithograpically. If you wanted to try an etch mask over the contacts to protect them during metal gate cut you run into the same EPE issues as placing the contacts that lead to wanting to self align them. It would defeat the point of self alignment.
For the various Intel and Samsung finFET nodes that have SAC (which I believe is all of them), the gate cut is before RMG so there isn't that incompatibility. The problem at that point is just litho reliably placing the poly cut far enough away from the fins that there is space for WFMs. For SF4 and Intel 4/3 this seems to work well enough. But GAA throws things for a loop because there is even less space for WFMs. Samsung "solved" the issue by not having WFMs or multi VT. Which is obviously not really a solution. Time will tell if 18A or SF 1.4 use gate cut pre (with SAC) or post RMG (no SAC).
