Intel Products Update

[Fred Chen]

The problem with SAC is etch. If you do your gate cut after RMG your etch needs to eat W but the contacts are also W. And the whole reason TSMC went with SAC was it was getting to hard to place the contacts lithograpically. If you wanted to try an etch mask over the contacts to protect them during metal gate cut you run into the same EPE issues as placing the contacts that lead to wanting to self align them. It would defeat the point of self alignment.

For the various Intel and Samsung finFET nodes that have SAC (which I believe is all of them), the gate cut is before RMG so there isn't that incompatibility. The problem at that point is just litho reliably placing the poly cut far enough away from the fins that there is space for WFMs. For SF4 and Intel 4/3 this seems to work well enough. But GAA throws things for a loop because there is even less space for WFMs. Samsung "solved" the issue by not having WFMs or multi VT. Which is obviously not really a solution. Time will tell if 18A or SF 1.4 use gate cut pre (with SAC) or post RMG (no SAC).

It seems you are referring to gate cut after SAC? That is very odd.

 

[nghanayem]

So a theory on this; it's not a priority because of risk/reward vs. other segments for AMD.

Intel is still doing some dirty tricks in this space; As recently as a few years ago, HP was still giving slightly higher model #s for Intel vs. AMD chips to subtly make them sound better (they may still be doing this), and the Intel-Dell relationship always has something going on.

Intel products isn't exactly well known for their stellar customer focus. But AMD seems worse in this regard. CCG worked with OEMs to develop technologies for new categories and has done work to level up OEMs to make the newish so--called "macbook compete" class of laptops. AMD seems to have a here's our chip please buy it go to market strategy. Funny because my understanding is in EPYC they did a lot of work to make the process more seamless and work with you to optimize systems and workloads.

AMD does have a few chips they *could* use for this market - the Ryzen Z2 series for example,

I don't think these are ideal. It is kind of tough because AMD doesn't have a Sawtooth or Skymont-LP equivalent. I really like the idea of Apple's 2 big core and 4 true little core arrangement. But if you must have performance, I feel like the 4+4 config is maybe a more well balanced core configuration for a laptop CPU. WIth that said, I wouldn't hate the idea of a 2+6 config especially if your little cores got a lot of grunt like skymont. But back to AMD because they don't have a true LP core (just a slightly more compact layout/synthesis) I feel like a true 15W and below segment CPU from AMD might be best served with a 2 Zen + 2 Zen C. If they must have "muh performance" give it 4 Zen C. The Zen C cores have a good bit of muscle to them but are a bit thirsty and big. IMO that calls for AMD using fewer cores than LNL. But the extra grunt from their cores should in theory make up for some of the core count deficit. The rest of the SOC has a lot of room for improvement too, but I don't even want to pretend to give suggestions on what to do better as I wouldn't have even the faintest idea.

but they haven't scaled up production or fleshed out enough SKUs for it.

This is part of my problem. AMD takes way too long to ramp client parts compared to Intel, QCOM, Nvidia, and MTK. For them a new product is out and within a year it is the majority of the volume. For AMD their ramps and deramps are so slow they never have a majority of volume product because the highest volume thing they have is like 30% of shipments. The biggest area of improvement I have seen is actually launching their laptop parts with the cycle rather than midcycle when no new laptops are launching and nobody is buying.

They also do have multiple monolothic chips that could be scaled down (the APUs); and yes I see you want a separate PCH but the power benefit of the fully integrated die is pretty powerful in this market.

Separate PCH while higher power hasn't stopped intel from beating AMD in low power. While easier said than done, AMD needs to "just figure it out". IMO AMD has no excuse for being so supply limited in laptop all the time. Either pay up with bigger prepay or minimize content on the leading edge node in places where it isn't too painful. A company with a P/E over 100 (like 3x NVIDIA or Apple levels) needs to be growing RAPIDLY, and AMD doesn't have the excuse of "little old AMD is too poor to compete with Intel" anymore.

I'm guessing AMD not seriously entering the U market is a calculated move -- like prioritizing N4 wafers for Epyc over Radeon.

That is easy though since Epyc has competitive strength, radeon doesn't. Additionally, the margins for DC CPUs are WAY higher than client GPUs. But like I have said before I think AMD has somewhat squandered their limited time with a process lead by not putting down bigger prepays and moving to new nodes sooner.

The U market is also where Intel is *most* competitive which means AMD would need to spend more $$ to take market share there than other spaces.

Maybe, that logic works back in the day. But now I don't buy it. AMD has tons of money and has had rapid stock growth. As for client, there is no more important market to invest in. That would be like if AMD said they weren't going to prioritize DC GPUs because they wanted to double down on taking market share from GeForce with Radeon. Yes maybe NVIDIA is easier to out do in client than DC, but looking at that market and saying you don't want to gun for it feels like bad business (especially when your stock price has so rapidly outpaced earnings growth).

It seems you are referring to gate cut after SAC? That is very odd.

Yes SAC has to be done fairly early in the process (and definitely before the replacement gate for it to even work). Doing gate cut pre RMG involves cutting the poly then placing a plug so it doesn't get filled back in during RMG. The poly cut and subsequent plug being too close to the fins is what is responsible for the WFM fill issues I mentioned. If you want to do your gate cut post RMG (like N5/N3E do) it is by extension after the contact formation. The benefit to doing cut after RMG is that you can have all the space you need to fill your WFM and W, then cut the gate with more margin for error.

The image is kind of screwed up because I drew the plug centered and too wide so it pinches both devices. Realistically the issue is when your EPE takes you to close to one of the devices and causing that WFM and W to not fully wrap around the edge of the fin. But the image at least shows the mechanism and how cutting a fully formed gate gives you more error margin to work with on your gate cut placement accuracy. Unfortunately I didn't realize my mistake until after I drew it so, it is what it is.

 

[Xebec]

I don't think these are ideal. It is kind of tough because AMD doesn't have a Sawtooth or Skymont-LP equivalent. I really like the idea of Apple's 2 big core and 4 true little core arrangement. But if you must have performance, I feel like the 4+4 config is maybe a more well balanced core configuration for a laptop CPU. WIth that said, I wouldn't hate the idea of a 2+6 config especially if your little cores got a lot of grunt like skymont. But back to AMD because they don't have a true LP core (just a slightly more compact layout/synthesis) I feel like a true 15W and below segment CPU from AMD might be best served with a 2 Zen + 2 Zen C. If they must have "muh performance" give it 4 Zen C. The Zen C cores have a good bit of muscle to them but are a bit thirsty and big. IMO that calls for AMD using fewer cores than LNL. But the extra grunt from their cores should in theory make up for some of the core count deficit. The rest of the SOC has a lot of room for improvement too, but I don't even want to pretend to give suggestions on what to do better as I wouldn't have even the faintest idea.

OT - but I really liked when AMD was doing the "cat" cores -- I had built a few low power Linux workstation/server systems around them (dirt cheap Athlon 5350, etc).

I agree they don't have full equivalents to Intel, though FWIW the "Ryzen Z2 Extreme" *appears to have* 3 x Zen 5 + 5 x Zen 5C cores. (Yes weird, but inbetween your 4+4 and 2+6 ). These are 28W TDP that can be limited further.

Googling Performance: "below HX 370 and Intel 258V, but within the same performance envelop" (presumably 28W TDP).

*appears because AMD doesn't specify the makeup on their website, but every other source I've checked indicates this configuration.

I'll have to do some analysis on Skymont vs. Zen 5C. Skymont has IPC in the range of Zen 3 or maybe slightly higher; and IIRC can actually clock (~20+%?) higher than Zen 5C.

I'll just add that I think the # of cores needed for laptop really depends on use case. A personal machine running basic background stuff (Windows+Defender) needs less "compact/cool/efficient" cores than a corporate laptop that can run as many as 50 independent security / forensics / update / logging / etc. agents (from various vendors) simultaneously.

When I worked at large corporations, it was a easier to meet security requirements on the Mac with a smaller # of unique tools than it was on Windows. That's a combination of pickyness by Cybersecurity firms, but also greater fragmentation of offerings too. That meant all things else being equal, a Macbook would be more performant than a Windows laptop. tl;dr - Apple doesn't need as many "e-cores" for corporate use as Windows typically does.

But like I have said before I think AMD has somewhat squandered their limited time with a process lead by not putting down bigger prepays and moving to new nodes sooner.

This is actually a historic recurring theme with AMD. They made the same mistake with the K8 chip where they talked about using "Chartered Semiconductor" to make K8-based server and desktop chips for a couple of years and then nothing ever happened. They limited their server and desktop marketshare through lack of capacity, even when they had a few years to run wild (2003-2006). There's an argument they made the same mistake with K7.

Maybe, that logic works back in the day. But now I don't buy it. AMD has tons of money and has had rapid stock growth. As for client, there is no more important market to invest in. That would be like if AMD said they weren't going to prioritize DC GPUs because they wanted to double down on taking market share from GeForce with Radeon. Yes maybe NVIDIA is easier to out do in client than DC, but looking at that market and saying you don't want to gun for it feels like bad business (especially when your stock price has so rapidly outpaced earnings growth).

This is in reference to the "U" market.

I still think the "U" market is more of an uphill battle for AMD right now vs. Intel than just expanding other segments:

- Desktops and Server - AMD has the mindshare already - there's no "ceiling"
- Servers are the highest margin, no questions - so priority #1
- Desktops are easy chips to share yields with server
- Intel has been consistently competitive in the U space forever, even when their server and desktop offerings are weak
- The U space requires a little more work than desktop for integration purposes
- "Nobody ever got fired for buying IBM" still exists in some form for buying corporate laptops from Intel

I'm 100% with you they need to go after this market, but I'm guessing the culture of not gambling on too much capacity and keeping engineering talent focused on "less better quality products" has them shying away from U vs. Server, Desktop, and high power mobile.

 

[siliconbruh999]

I'll have to do some analysis on Skymont vs. Zen 5C. Skymont has IPC in the range of Zen 3 or maybe slightly higher; and IIRC can actually clock (~20+%?) higher than Zen 5C.

Skymont has IPC slightly higher than Zen4/Raptor Cove

 

[Xebec]

Skymont has IPC slightly higher than Zen4/Raptor Cove

Integer - Yes, though I think FP is significantly weaker?

I need to research a bit further

 

[XYang2023]

Integer - Yes, though I think FP is significantly weaker?

I need to research a bit further

With FP, there is Xe2 core.

 

[siliconbruh999]

Integer - Yes, though I think FP is significantly weaker?

I need to research a bit further

With FP, there is Xe2 core.

He meant CPU FPU not the GPU