I am a bit surprised that their SAC would get in the way of their gate cut. Granted that it's getting very tight there. The directly focused spot size of EUV is 25 nm, so it's too large for the contact sizes I was expecting.
The problem with SAC is etch. If you do your gate cut after RMG your etch needs to eat W but the contacts are also W. And the whole reason TSMC went with SAC was it was getting to hard to place the contacts lithograpically. If you wanted to try an etch mask over the contacts to protect them during metal gate cut you run into the same EPE issues as placing the contacts that lead to wanting to self align them. It would defeat the point of self alignment.
For the various Intel and Samsung finFET nodes that have SAC (which I believe is all of them), the gate cut is before RMG so there isn't that incompatibility. The problem at that point is just litho reliably placing the poly cut far enough away from the fins that there is space for WFMs. For SF4 and Intel 4/3 this seems to work well enough. But GAA throws things for a loop because there is even less space for WFMs. Samsung "solved" the issue by not having WFMs or multi VT. Which is obviously not really a solution. Time will tell if 18A or SF 1.4 use gate cut pre (with SAC) or post RMG (no SAC).
I do see the power benefit on Lunar Lake though with the IMC being on the Compute Tile. I was mistaken thinking it was on the Platform I/O tile like Arrow Lake (And Ryzen).
Minor correction: the IMC was on the SOC die rather than the io/PCH die.
Sorry I was referring to the process tech. Backside Power Delivery, GAAFET, to achieve no improvement in efficiency based on Intel's wording of "power efficiency of Lunar Lake".
Just because PNL isn't wildly more efficient than N3 doesn't mean 18A isn't an improvement. ARL on N3 wasn't meaningfully better than Intel 4 MTL and didn't have better performance than i7 desktop parts. BSPDN also isn't a gigantic performance enhancement. IMO the largest benefit is freeing up routing space as well being necessary for future process node scaling. As for GAA power performance it isn't as big of a boon as finFET (just look at N2). Makes sense at a high level too. At risk of over simplifying finFETs added 2 gate interfaces while GAA only adds 1 and you lose A LOT of carrier mobility.
I suspect Panther Lake is going to be more expensive over it's life time
Maybe circa January 25 it was more expensive. But circa January 26 it shouldn't be. one would hope the head of CCG knows how much her chips cost
than Lunar Lake to manufacture based on using a ~mature N3 node vs. ramping 18A. Nova Lake will get the benefit of a mature 18A node of course.
SInce most laptops launch in starting in January 18A should be very mature by the time PNL starts making up a large fraction of total unit shipments.
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I still think the bar is really low on Panther Lake because they're basically just describing a scaled up Lunar Lake with no efficiency gains. I can understand why some might say "this is OK", though as it's giving up the closely coupled memory and perhaps more and still achieving equivalent efficiency.
I think this metaphor I thought of while at work paints a decent analogy. Take the biggest baddest Dodge engine you can think of. Slam it into a Pacifica (and I recently learned yes apparently that is a real car for some ungodly reason). Then take like a BRZ or tuned up Miata. Which car will run a test circuit faster. On paper the Chrysler's got WAY more horsepower and probably better 0-60 and top speed. But the nimbler BRZ can corner much better with its better steering, transmission, balance, lower center of gravity, weight, etc. I'm not enough of a car guy to say what will be better (although I suspect it is very course dependent). But I think it illustrates the idea. The node is only one part of the story. If a good node was all one needed for a good chip, every smartphone today would be using an Intel CPU. At risk of getting a little lost in the sauce by returning to the car metaphor. If an apple Mx SOC is the 911, then LNL is the Cayman, and PNL is like the WRX. Yeah the Cayman or 911 is sportier but that doesn't mean WRX is bad. The WRX is aiming for a different market, is still a beloved driver's car that is also more practical, and affordable.
PNL is seemingly trying to take lessons learned from LNL and scale them across Intel's line up and bring that LNL goodness to the masses.
As a consumer/enthusiast -- Panther Lake (the CPU side) already sounds disappointing to me as a product as it doesn't appear to move the needle in any meaningful way that matters to an end user (the customer). If it doesn't matter to customers it won't help Intel.
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I mean they are cheaper to produce and will presumably be in cheaper/more laptops. Which is nice. Because even though Intel is practically subsiding OEMs to use LNL, LNL laptops aren't exactly cheap. But if as an enthusiast I doesn't light your fire, there is nothing I can do to change that. After all nobody can tell how you feel or how you should feel. I can certainly understand the disappointment after ARL was RPL again again but lower power and more money. Getting RPL performance in 2025 3 years after RPL doesn't feel right. But if it gives that perf with less power and cost. I am all for it, because I think lower cost and power is what Intel needs to succeed.
I do agree AMD has been slow on SoC's but they seem to be following 3-4 year cycles instead of 2 years like server/desktop. Strix and Strix Halo are pretty substantial improvements on their SoC recipe; and they have some pretty good looking Zen 6 based APUs coming end of next year. RDNA4 also looks like a "pause" that focused on efficiency that will make it's way down into the SoCs next generation too.
Performance of Strix and Halo isn't my problem. My problem is idle/low utilization power, high minimum TDP, price, availability. Are there improvements, sure. But they are incremental. I feel AMD's limited die configurations shoots themselves in the foot. And they picked the wrong segments to target. I think they need a 2+2 config that fully ditches the race to idle mindset, has a separate PCH to minimize cost and maximize unit shipments from limited wafer allocation, better lower power uncore, and more frequent updates to match OEM design cycles. Not a CPU designer ofc so take my opinion with a grain of salt. But as it stands AMD doesn't have a real U or V series competitor. And that is like what 80% of the laptop market? Niche how performance parts aren't what the market wants and Qualcomm has proved it in spite of all of the ankle weights they are dragging. If the rapid rise of Qualcomm doesn't show that AMD has been squandering the openings they've had in laptop I don't know what does.
. I was confusing the versions of ARL, (though the Intel comment didn't specify what performance level of Arrow Lake they were referring to).
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