Well, you have mastered the old Intel pitch perfectly.
Genuinely, what pitch would that be? I don't think refusing to drink the TSMC Kool aid of "they have always been the best technology company in industry and everything they do or have ever done is perfect" counts as an "Intel pitch". That is just being realistic about what is good and what could use improvement. It should be controversial to say that even a company as great as TSMC isn't perfect or infallible. After all if TSMC truly thought that they wouldn't constantly be upping their game year after year. DO NOT misunderstand me, I am NOT saying TSMC's empire is on the verge of crumbling, NOR do I think their status as the #1 foundry, or as the provider of the industry's best service are going anywhere either. All I am saying is based on the statements of intel/TSMC on how their processes stack up aligning, intel replacing N3 chips with 18A ones but rumored to use N2 over 18A-P for low volume highest power SKUs, and what ecosystem/customers say... 18A seems to fall squarely in the middle between N2 and N3P. It is also indisputable fact (source the VLSI papers detailing exactly this information) what I said about cell sizes, SRAM, and the benefits of BSPDN. There is nothing theoretical or design dependent about physically how big the devices and their wiring is. I also don't think it is incorrect or disingenuous to make the observation that IF 18A is between N3E and N2, AND intel is rolling out new full nodes every 2 years vs TSMC's trend of every 3 years, THEN it would appear that TSMC is falling behind.
Unfortunately that pitch is headed to the unemployment line.
Making the observation that Intel's process technologies from objective information look to be more advanced than TSMC's has nothing to do with foundry success or failure.
"Finally it is a fact that the 14A over 18A PPA uplift is bigger than the N3E to N2 uplift and slightly bigger than the N2 to A14 uplift."
This "fact" is based on your interpretation of ever changing marketing slides.
It is a fact that Intel's goal is higher than TSMC's final goal. Intel said they strongly believe they can do better than that commitment this year, and the fact that Intel has met or exceed almost every public PPA target they have set in the past 5 years should give some credibility to those claimed PPA targets panning out just as one would assume that TSMC will hit their PPA targets on a given technology.
Experienced semiconductor professional know better than to do this.
And I am not an experienced semiconductor professional? At the risk of this coming out worse than I intend, on this forum, I can't think of many people forum with experience as a process engineer in a process development organization? On EDA or ASICs I have no qualms deferring to a more knowledgeable person such as your self. But when it comes to discussions on process technology, I'd like to think that my moderate amount of experience holds some weight?
If a fabless foundry team used your "facts" in determining which process to use they would be unemployed.
It is a fact that both 1.4nm class process nodes are still in development, so A) the PDK won't be done yet and B) the PDKs as they exist today will be modeling the performance of the transistors as they exist TODAY. So comparing PDK performance today between currently in development process nodes would tell you nothing about the final end state. Unless you have a time machine, the only indication any customer could have is what the final targets are and how the foundry is tracking at various check points along the way to see if they think the foundry will hit those goals in the end. I figured with your background in EDA, you would have known that. Regardless, until the A16 and 14A PDKs hit 1.0 status, using PDKs to determine which process is "better" is a worse analytical method than
extrapolating from the final targets. In short since there is no PDK at the beginning of process development and even when there eventually is a PDK, it describes a process that isn't indicative of the final PDK revisions or what the final wafers will look like. Designers have to work from the process definition, how the foundry is tracking towards the various milestones along the way, and their trust in their foundry's execution when evaluating a technology. Mostly this work is done by foundry engagment engineers who are generally process engineers who often worked at the same fab. These engineers then work with their foundry colluges to go through the above information and use their expereince to inform their reports to the actual designers making wafer agreement decisions. Give an experienced process engineer a flow, some device models, DD/performance/variation trends, and some TEMs, and he can tell you anything you could ever want to know about how good the process is just with his eyes. He can see where others screwed up, what is innovative, what is mediocre, what is obsolete, and what is downright bad. Even with just a disection I have seen others can figure out with a remarkably high degree of accuracy where things stand. Even I can see it to some degree, and I haven't ever worked in process intergration or defmet.
To show an example why this is the best window into how final chips will shake out when the processes are still deep in development, let's take process A and process B with identical final PPA. Let's say at HVM-2 years the performance is at 70% of the final target and PDK 0.5 is supposed to drop, and that at HVM-3 performance is at 50% and PDK 0.1 is supposed to drop. Now let's say process A is due to start HVM 1 year ahead of process B. If you wanted to do a PDK comparison 2 years ahead of process A HVM, then process A would appear to have 40% greater PPA than process B when those processes are really perfectly matched.
But forget extrapolations, do you honestly believe that 14A will so horribly miss targets that it cannot make the tiny jump from 18A to N2? Even if we assume 18A is really exactly like N3P instead of slightly better, we are literally taking about 14A being less than 10% performance over 18A here Dan. Even if they bungled 14A, it would be hard to screw up
that bad.
In the trenches the PDK is where the rubber meets the road. The other idiom we use here in the trenches is "the proof is in the pudding" and thus far you have no pudding.
While I agree with your claim in broad strokes, this statement feels far too hand wavy to me. On a tangential note, my favorite quote on the topic of tracking process development progress and evaluating process technologies is from a big wig at a top 10 fabless design house I heard was "PDKs, models, and final performance targets don't mean much to me. I want to listen to the transistors... Because silicon, silicon never lies.".
But I am glad you are open to learning. Pro tip, if you ask questions your learning will accelerate.
Asking questions to people who know better than me is how I gain knowledge and experience so quickly. I also find it highly rewarding learning things I didn't know before.