Intel Employees "Very Optimistic"
- Thread starter Artificer60
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user nl
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It seems to me that the flexible and connected-GigaFab approach of TSMC in Arizona may be a key strategic success as it enables TSMC to adapt to the changing political dynamics and market demand while still over time benefit from that local economy-of-scale of having all those 6Phase-production capacity in a single location.
The present coercion-based Trump-2.0 administration "renegotiation" now uses a 4% upper-bound ChipsAct support level (from 10% before under Biden) to squeeze out more commitments. So, the 6.6 B$ that TSMC was awarded by Biden in 2024 (6.6/0.1 = 65 B$) is rescaled now to 6.6/0.04 = 165 B$ investment, the amount that CC Wei announced early March 2025 at the White House.
If Intel is held to that 4% threshold as well it needs to invest 8.5/0.04 = 212 B$ the coming years. Spread over 4 locations. Interesting! Who is going to pay for those Intel investments?
It seems that PG was perhaps more sensitive to the political (US-spread the pork) aspect of investing in all these different locations/states, whereas TSMC kept their economy-of-scale business case in sharp focus by dumping all that 6.6 B$ in supporting just a single connected GigaFab in Arizona growing over time from 1 Phase to 6 Phases&2Advanced packaging&R-D-Centre.
EUV-GigaFab single location foundry may be another strategic asset for TSMC's success versus Intel's multi-location (Oregon, Arizona, New Mexico, Ohio) strategy the coming decade?
The battle TSMC versus Intel Foundry has so many dimensions, it seems like a very interesting academic topic for a second book on Chip War! Chris Miller are you working on the sequel yet
?https://www.theverge.com/24166234/chips-act-funding-semiconductor-companies
https://www.theregister.com/2025/06/05/trump_chips_act/
"I think commitments of 4 percent or less are more appropriate than a 10 percent funding — it just seemed overly generous — and we've been able to renegotiate them," Lutnick said, praising the additional commitment. "The only deals that are not getting done are deals that should have never been done in the first place."
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I don’t think there’s any point in acknowledging the 4% threshold. Intel already has enough issues to address—what it needs to focus on is profitability.It seems to me that the flexible and connected-GigaFab approach of TSMC in Arizona may be a key strategic success as it enables TSMC to adapt to the changing political dynamics and market demand while still over time benefit from that local economy-of-scale of having all those 6Phase-production capacity in a single location.
The present coercion-based Trump-2.0 administration "renegotiation" now uses a 4% upper-bound ChipsAct support level (from 10% before under Biden) to squeeze out more commitments. So, the 6.6 B$ that TSMC was awarded by Biden in 2024 (6.6/0.1 = 65 B$) is rescaled now to 6.6/0.04 = 165 B$ investment, the amount that CC Wei announced early March 2025 at the White House.
If Intel is held to that 4% threshold as well it needs to invest 8.5/0.04 = 212 B$ the coming years. Spread over 4 locations. Interesting! Who is going to pay for those Intel investments?
It seems that PG was perhaps more sensitive to the political (US-spread the pork) aspect of investing in all these different locations/states, whereas TSMC kept their economy-of-scale business case in sharp focus by dumping all that 6.6 B$ in supporting just a single connected GigaFab in Arizona growing over time from 1 Phase to 6 Phases&2Advanced packaging&R-D-Centre.
EUV-GigaFab single location foundry may be another strategic asset for TSMC's success versus Intel's multi-location (Oregon, Arizona,Ohio) strategy the coming decade?
The battle TSMC versus Intel Foundry has so many dimensions, it seems like a very interesting academic topic for a second book on Chip War! Chris Miller are you working on the sequel yet
https://www.theverge.com/24166234/chips-act-funding-semiconductor-companies
https://www.theregister.com/2025/06/05/trump_chips_act/
"I think commitments of 4 percent or less are more appropriate than a 10 percent funding — it just seemed overly generous — and we've been able to renegotiate them," Lutnick said, praising the additional commitment. "The only deals that are not getting done are deals that should have never been done in the first place."
Additionally, many of these analyses fail to consider external factors:
Some media outlets in Taiwan interpreted it as the U.S. leaving Taiwan on its own.
user nl
Active member
Adding to my point, the TSMC-Intel foundry battle is so multi-dimensional! My post about the 4%-Trump chips-norm addresses only one of those dimensions.
Many dimensions to weigh for Intel's new CEO. LBT recently said (when accepting an award) that being Intel's CEO seemed 50 times more difficult than being Cadence's CEO. The future will tell us how history will look back on his "new" strategy weighing all those dimensions and his execution. We are in the easy and comfortable arm chair position commenting on all this from the sideline (?) (at least for me) at SemiWiki (thanks Dan and team!)..........
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To solve a problem, one approach is the reduce the dimensionality of the problem. Ultimately the value of a company is determined by pnls. The problem for the CEO of a company is to drive up pnls/valuation. That should be the focus.
siliconbruh999
Well-known member
Well Cadence is only an EDA company unlike Intel which is a rare case of a leading edge logic IDM with so many stuff Cadence don't compare to Intel's complications.
user nl
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Some of the discussion here relates to Products, some to Foundry. Doesn't this not suggest that at some point the key strategic discussion/decision is : how to operate Product and Foundry completely independent, to the benefit of both? Only the timing (when 14A comes to market?) and the "divorce-settlement" are the big unknowns?
user nl
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I do not know any of the people and have no history in the semi-industry (just an arm chair observer, who occasionally likes to comment on strategic versus tactical issues). When long term strategy may appear outdated/wrong/unknown the tactical issues may be a waist of resources and energy?
PG, as a former trainee of one of the Intel-Trinity (as commented by siliconbruh999 elsewhere in this thread before), came back as CEO, initiated the first steps toward the divorce-settlement by completely separating the financial operations of Product and Foundry during 2023-2024. It must have been emotionally (?) almost impossible for him, being groomed by the Trinity, to divorce Intel Product & Foundry.
Will the next steps be toward a final divorce (either by LBT or his successor) to the benefit of both "parents"? Will their "children" (the employees) all be treated equally and fairly? Is their already growing-and-growing unrest among the various children that are still "living at home"? Some may have left their parental home already in various waves during 2023-2024.
LBT from his passed professional career seems most interested in start-ups. Will LBT give his interest/knowledge/experience to "parents Product and Foundry" to become two newly "divorced start-ups" when 14A hits the market?
Interesting business case for him to decide with his Board and management team.
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siliconbruh999
Well-known member
I don't think the problem for Intel is strategy it's been execution.
10nm/14nm
Skylake stagnation
GPUs
Yea, he was under Andy Grove
Why not both Foundry and Product both have value why destroy it?
user nl
Active member
A real "divorce" not aimed to destroy one or both of the "parents", but to let both "parents" blossom (unlock their independent value) again. Their "personal and relational" issues may have existential effects on one or both of the "parents"?
It seems quite some financial people in Intel's board presently. Like it's current chairman, presently managing partner at Darwin, after being at another financial advisors company till 2018, that was sold to Darwin in 2018 for some 165 M$. Not a PhD in semi-research (like CC Wei).
Darwin (what's in a name?): Connecting entrepreneurs and investors, we serve companies and startups in various stages of development with all the experience necessary to ensure their success. (https://darwin.capital/en/the-company/)
However, financing start-ups seems a different sport than financing one of the most capital-intensive industries like EUV-foundries, I would think.
To me, the long-term strategic vision of the newly appointed (Dec 2024!) Intel Board member Eric Meurice seems most of interest. Meurice, a European (foreigner and global professional citizen) who as CEO and Board Chairman (during 2004-2014) of semi company ASML, transformed ASML to an effective litho-monopolist, after beating the Japanese litho-stars Nikon and Canon on their playing field:
https://newsroom.intel.com/biography/eric-meurice
Meurice has nothing to prove anymore, neither as CEO, nor as a Darwanian start-up financer.....
@Dan: could you have a chat with Eric Meurice someday?
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No agenda Dan, just the facts as I see them. 18A is cranking chips out now, and neither TSMC nor Samsung's customers/internal are launching any 2nm products this year. It is also an objective fact that 18A is first to BSPDN by a wide margin (looking like a 2 year lead in TTM vs A16 given A16 HVM is in 2H26). Based on the DD curves shown, test chip yields quoted by TSMC, and common sense Intel seems a bit ahead of N2 DD (not surprising given 18A went to HVM a year earlier and that TSMC yield wasn't as much of a priority until last year with a likely rapid closing of the gap likely over this and next year), and Samsung seems woefully behind given they still haven't launched a GAA mobile AP. So with that information I suppose you could also say 18A is also the first high yield commercial GAA process even though I would be hesitant to award that title when the 3GAP smartwatch chip exists in the millions in all of its 17mm2 of embarrassment.
Additionally 18A has denser SRAM than N3, smallsr HP logic cells, HD logic cells that are 3% larger, and for power grid limited designs TSMC and Intel both agree that BSPDN can additionally confer up to a 10% shrink on real IPs. Furthermore based on Intel's comments that 18A power performance is "comparable" to N2 and better than N3, and TSMC's that N3 is "comparable" to 18A with N2 being the most advanced process in the world when it launches; TSMC and Intel's public statements based on where customers tell them each others processes are seem to align that Intel leads in 2025, and it isn't until 2026 that TSMC strikes back. Of course purely from a technology perspective because that is what you called "a pipedream".
Finally it is a fact that the 14A over 18A PPA uplift is bigger than the N3E to N2 uplift and slightly bigger than the N2 to A14 uplift. Since I have already established that 18A is a higher baseline than N3P, and more importantly for this point without a shred of doubt a higher baseline than N3E. That means that in 2027 14A should take TSMCs 2026 lead back from N2/A16 until the first A14 products come to an iPhone near you in 2029. That is two full years as the process leader even if 10A isn't just better than A14 (which it might well be given A14 is only a slightly bigger boost than N2 was/is over N3E and Intel is operating at a bigger baseline).
If you want say Intel as a foundry services provider is nowhere near touching TSMC anytime soon, sure no arguments there. Intel getting to that level is a long way in the future (if it ever happens at all). But from a "Moore's law" perspective Intel is clearly on the precipice of achieving the goal Intel set out to achieve with 5N4Y, and once again taking up their mantle as the heartbeat of transistor innovation. If you have a factual or an evidence based argument that indicates a flaw in my analysis I am all game to hear it, as I see being wrong as a learning opportunity.
user nl
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What is your opinion regarding (long-term) completely separating Product and Foundry, in view of all your technical expertise?
And some people say (Intel's) Moore's law is becoming more and more a (TSMC's?) 3D-law (including photonics) the coming decade?
They already are separated in a sense as independent subsidiaries. So to each other I don't think it makes a big difference. But to the wider Intel corp I think it sounds like a poor idea assuming Intel foundry can break even reasonably soon. Dumping one or the other will reduce the company's margins if Intel foundry can even get 1% operating margin. I also have little confidence in the design side execution versus the manufacturing side which has been the most reliabile and successful part of the company. Even putting that issue aside I think foundry offers the single greatest growth opportunity to Intel since the PC. Intel no longer has to anticipate the future of computing (something they historically are inept at), and can instead grow with the overall semi market rather than being beholdent to the saturated markets like PCs. As for long term reasons for why Intel foundry would want to be part of Intel corp, that is harder to see the benefit. I guess mainly having the two in one entity allows for greater diversification and products which is capital light allows an integrated Intel corp to be less heavily levered.
That is absurd. Intel doesn't own transistor innovation nor does TSMC doesn't own 3D (their place in the space is overstated and not reflective of the actual advanced packaging space. People talk like OSATs don't do it at all, and that IDMs like Micron, SK, and Intel don't run more advanced packaging unit volume than TSMC. Photonics don't reduce cost, and advanced packaging doesn't really reduce cost per function by very much. Rather it allows for total energy/TCO to go down and design reuse/fungibility. Transistor innovation and continued cost per FET reductions (because counter to the often misreported narative cost per FET is still happening) and packaging innovation are complementary and both necessary.
user nl
Active member
Many thanks, for your view. Would external Foundry customers not see this as a potential negative? Intel Products (with whom they compete) is needed to keep Intel Foundry afloat, where they have their competing products made.
My apologies, no offense to you or anyone in this industry. Playing "devil's-advocate" from my arm chair.......but having a lot of past professional (academic and entrepreneurial) experience with photons (not in semi-industry).
If you truly believe that, then nothing I say is going to make any difference to you. But I would not call it sound analysis to extrapolate changes Pat Gelsinger drove inside Intel based on his post-retirement activities and his beliefs in his personal life.
But I don't know, stuck at 10nm to Intel 18A (through 5N4Y) is a spectacular focus on getting Intel competitive again to me personally.
We will need to see how PTL, CWF, ARC C & D series, NVL and DMR performs to really see what Pat Gelsinger's Intel is imho.
Well, you have mastered the old Intel pitch perfectly. Unfortunately that pitch is headed to the unemployment line.
"Finally it is a fact that the 14A over 18A PPA uplift is bigger than the N3E to N2 uplift and slightly bigger than the N2 to A14 uplift."
This "fact" is based on your interpretation of ever changing marketing slides. Experienced semiconductor professionals know better than to do this. If a fabless foundry team used your "facts" in determining which process to use they would be unemployed. In the trenches the PDK is where the rubber meets the road. The other idiom we use here in the trenches is "the proof is in the pudding" and thus far you have no pudding.
But I am glad you are open to learning. Pro tip, if you ask questions your learning will accelerate. Pontificating does not work as well.
Genuinely, what pitch would that be? I don't think refusing to drink the TSMC Kool aid of "they have always been the best technology company in industry and everything they do or have ever done is perfect" counts as an "Intel pitch". That is just being realistic about what is good and what could use improvement. It should be controversial to say that even a company as great as TSMC isn't perfect or infallible. After all if TSMC truly thought that they wouldn't constantly be upping their game year after year. DO NOT misunderstand me, I am NOT saying TSMC's empire is on the verge of crumbling, NOR do I think their status as the #1 foundry, or as the provider of the industry's best service are going anywhere either. All I am saying is based on the statements of intel/TSMC on how their processes stack up aligning, intel replacing N3 chips with 18A ones but rumored to use N2 over 18A-P for low volume highest power SKUs, and what ecosystem/customers say... 18A seems to fall squarely in the middle between N2 and N3P. It is also indisputable fact (source the VLSI papers detailing exactly this information) what I said about cell sizes, SRAM, and the benefits of BSPDN. There is nothing theoretical or design dependent about physically how big the devices and their wiring is. I also don't think it is incorrect or disingenuous to make the observation that IF 18A is between N3E and N2, AND intel is rolling out new full nodes every 2 years vs TSMC's trend of every 3 years, THEN it would appear that TSMC is falling behind.
Making the observation that Intel's process technologies from objective information look to be more advanced than TSMC's has nothing to do with foundry success or failure.
It is a fact that Intel's goal is higher than TSMC's final goal. Intel said they strongly believe they can do better than that commitment this year, and the fact that Intel has met or exceed almost every public PPA target they have set in the past 5 years should give some credibility to those claimed PPA targets panning out just as one would assume that TSMC will hit their PPA targets on a given technology.
And I am not an experienced semiconductor professional? At the risk of this coming out worse than I intend, on this forum, I can't think of many people forum with experience as a process engineer in a process development organization? On EDA or ASICs I have no qualms deferring to a more knowledgeable person such as your self. But when it comes to discussions on process technology, I'd like to think that my moderate amount of experience holds some weight?
It is a fact that both 1.4nm class process nodes are still in development, so A) the PDK won't be done yet and B) the PDKs as they exist today will be modeling the performance of the transistors as they exist TODAY. So comparing PDK performance today between currently in development process nodes would tell you nothing about the final end state. Unless you have a time machine, the only indication any customer could have is what the final targets are and how the foundry is tracking at various check points along the way to see if they think the foundry will hit those goals in the end. I figured with your background in EDA, you would have known that. Regardless, until the A16 and 14A PDKs hit 1.0 status, using PDKs to determine which process is "better" is a worse analytical method than extrapolating from the final targets. In short since there is no PDK at the beginning of process development and even when there eventually is a PDK, it describes a process that isn't indicative of the final PDK revisions or what the final wafers will look like. Designers have to work from the process definition, how the foundry is tracking towards the various milestones along the way, and their trust in their foundry's execution when evaluating a technology. Mostly this work is done by foundry engagment engineers who are generally process engineers who often worked at the same fab. These engineers then work with their foundry colluges to go through the above information and use their expereince to inform their reports to the actual designers making wafer agreement decisions. Give an experienced process engineer a flow, some device models, DD/performance/variation trends, and some TEMs, and he can tell you anything you could ever want to know about how good the process is just with his eyes. He can see where others screwed up, what is innovative, what is mediocre, what is obsolete, and what is downright bad. Even with just a disection I have seen others can figure out with a remarkably high degree of accuracy where things stand. Even I can see it to some degree, and I haven't ever worked in process intergration or defmet.
To show an example why this is the best window into how final chips will shake out when the processes are still deep in development, let's take process A and process B with identical final PPA. Let's say at HVM-2 years the performance is at 70% of the final target and PDK 0.5 is supposed to drop, and that at HVM-3 performance is at 50% and PDK 0.1 is supposed to drop. Now let's say process A is due to start HVM 1 year ahead of process B. If you wanted to do a PDK comparison 2 years ahead of process A HVM, then process A would appear to have 40% greater PPA than process B when those processes are really perfectly matched.
But forget extrapolations, do you honestly believe that 14A will so horribly miss targets that it cannot make the tiny jump from 18A to N2? Even if we assume 18A is really exactly like N3P instead of slightly better, we are literally taking about 14A being less than 10% performance over 18A here Dan. Even if they bungled 14A, it would be hard to screw up that bad.
While I agree with your claim in broad strokes, this statement feels far too hand wavy to me. On a tangential note, my favorite quote on the topic of tracking process development progress and evaluating process technologies is from a big wig at a top 10 fabless design house I heard was "PDKs, models, and final performance targets don't mean much to me. I want to listen to the transistors... Because silicon, silicon never lies.".
Asking questions to people who know better than me is how I gain knowledge and experience so quickly. I also find it highly rewarding learning things I didn't know before.
I think you misunderstand. That last bit you quoted was my saying what benefit does Intel foundry get from being in Intel corp. I think once breakeven occurs, Intel corp benefits more from foundry than foundry benefits from intel corp. But to answer your actual question no. Samsung has a similar albeit less extensive split with their manufacturing and design arm and even fierce competitors have no problem giving their crown jewels to Samsung. If you stole a design or prioritized intel product wafers over existing commitments to external customers it would be the last customer you would ever have. Considering the customers who have publicly mentioned kicking the tires on intel's processes/running testchips, clearly actual fabless firms are not concerned about IP theft. Right now the fact that intel foundry need products to pay to keep the lights on I'm sure is very concerning to customers. But from a "will you even be in business by the time our product is done being designed perspective and are we better off just waiting until we are sure intel foundry isn't going anywhere?" way. Once intel breaks even and has their fab footprint modernized and EUV capiable, then Intel foundry will obviously become less heavily levered/will have a clearly sustainable business. But it is also true that Intel foundry will always benefit being part of a larger entity with more revenues in a higher margin business (because generally chip design is more profitable than foundry) to make getting cheaper loans or just using cash on hand to fund future expansions.
No apologies needed. If anything, I should be apologizing to you for being intimidating. I didn't have any malice in my words. Oftentimes, my talk is more blunt or harsh than I intended for it to come out. It is something I want to become better at. As for photonics specifically. As weird as it sounds, honestly it seems like GF leads the way on photonics. They have been doing it for longer than TSMC, who only recently really started doubling down on it once it became a big enough market for them to attack. And in typical Intel fashion, the implementations they have shown off over the years have been sitting on the cool things Intel foundry makes, but Intel products didn't use so it sat on a shelf camp. UMC isn't really a big player in the space either, nor is TI, nor the memory guys. Even small boutique foundries who actually have very good niche process tech (especially in the field of SiPho) like Tower doesn't seem to have as much customer traction as GF. But it is a field in its infancy and now that TSMC is treating this as a major focus area, I'm sure they will play an increasingly important role in SiPho and then build a nice big sandbox all to themselves like they did with COWOS.
A 2 year 7 month stint in Dry Etch does not constitute a moderate amount of semiconductor experience on this forum. Fred Chen, for example, has a PhD in Applied Physics from Cornell and 30 years of experience in process technology. Have you every seen me disagree with Fred? No because Fred knows what he is talking about.