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The first Panther Lake engineering samples, made with Intel/IFS’s 18A, are currently being tested by major PC ODM/EMS makers. My early 2025 industry survey showed 18A yields below 20-30%, so there’s still a lot of room to step up—which doesn’t bode well for Intel’s goal of hitting mass production in 2H25. On top of the tech challenges, IFS faces a big obstacle in winning outside orders due to its org setup, supply chain mgt, and culture. That’s where TSMC totally stands out.
Curious how he can do survey on the yields. Thought Intel would send the functional chips to each clients with a few grades like U9, U7, and U5. Does he use the number of U9 chips divided by the total number of chips intel clients get? If that is the case, 20-30% yield is actually superb.
I know I am dumb, but someone please teach me on this.
Curious how he can do survey on the yields. Thought Intel would send the functional chips to each clients with a few grades like U9, U7, and U5. Does he use the number of U9 chips divided by the total number of chips intel clients get? If that is the case, 20-30% yield is actually superb.
I know I am dumb, but someone please teach me on this.
the yield numbers could be anything. SRAM, Non-redundant SRAM, Panther lake.... with and without known circuit fixes. Intel should worry about them, Other people should not. Could also be % of working PC test vehicles with Panther lake.... who knows. Its still ES so all bet are off.
Curious how he can do survey on the yields. Thought Intel would send the functional chips to each clients with a few grades like U9, U7, and U5. Does he use the number of U9 chips divided by the total number of chips intel clients get? If that is the case, 20-30% yield is actually superb.
I know I am dumb, but someone please teach me on this.
Ming-Chi Kuo and his yield survey are full of manure. 18A yields are on track to what they told us last December. From what I have heard there will be external customer 18A tape-outs in 2H 2025 and I have not heard one complaint about yield. In my opinion packaging is much more likely the cause of delays. Multi die packaging is HARD (thermal issues) and we really have just begun. Just ask Nvidia.
I'm not sure why everyone is getting their clicks by bashing Intel but it is an absolute abuse of media. The whole media landscape seems to have lost their way. I really expect better from tech pubs.
Ming-Chi Kuo and his yield survey are full of manure. 18A yields are on track to what they told us last December. From what I have heard there will be external customer 18A tape-outs in 2H 2025 and I have not heard one complaint about yield. In my opinion packaging is much more likely the cause of delays. Multi die packaging is HARD (thermal issues) and we really have just begun. Just ask Nvidia.
I'm not sure why everyone is getting their clicks by bashing Intel but it is an absolute abuse of media. The whole media landscape seems to have lost their way. I really expect better from tech pubs.
So let's see if 18A yields were 10% in December and are 25% (average) in February, then by EOY when they launch they will be at near 100% assuming that rate of improvement. I know yield rate improvement is non-linear but if we are going to look at spurious numbers to begin with why not go all in and take this to the extreme.
Yeah, it was not intended to be taken seriously. I thought it was sufficiently over the top that it would be obvious I was joking. Apparently not, my bad.
Yeah, it was not intended to be taken seriously. I thought it was sufficiently over the top that it would be obvious I was joking. Apparently not, my bad.
So let's see if 18A yields were 10% in December and are 25% (average) in February, then by EOY when they launch they will be at near 100% assuming that rate of improvement. I know yield rate improvement is non-linear but if we are going to look at spurious numbers to begin with why not go all in and take this to the extreme.
Did you mean a lot or a wafer? Perfect wafers in my experience aren't too rare on a 4+ year old process. For a whole 25w lot, yeah that is pretty hard. I bet it isn't too hard to find a passive interposer lot that is perfect though. They are comically simple and perfect wafers are almost an expectation (especially when we are talking 8x reticle stitched dies).
Did you mean a lot or a wafer? Perfect wafers in my experience aren't too rare on a 4+ year old process. For a whole 25w lot, yeah that is pretty hard. I bet it isn't too hard to find a passive interposer lot that is perfect though. They are comically simple and perfect wafers are almost an expectation (especially when we are talking 8x reticle stitched dies).
I had worked in Fab manufacturing for near 30 years. Interposer is quite simple/few layer processes and yes could be quite possible to have 100% yield for few but not many "lots". But the baseline yield could be greater than 95% in this large die size.
