Does IC design houses contribute significant IP or advise for advanced packaging?

[VCT]

Does TSMC have some edge for advanced packaging development over Intel and Samsung because TSMC's customers such as AMD and Apple work with TSMC for advanced packaging?

 

[james juang]

For the development of a new process, it requires close cooperation between process and design teams. Process engineers can only do that much. The last mile in tuning the yield must come from the inputs of a very experienced design team. It is not entirely accurate to say Samsung vs TSMC in leading-node competition rather should be Samsung vs (Apple +TSMC).

It is even more interesting for the development of 3D packaging. Japanese companies provide most packaging materials and equipment. And now TSMC Tsukuba 3D packaging center is operational., and there are 25 Japanese equipment and material companies joining in. The whole flow has become Apple and AMD are throwing out and testing all kinds of new packaging ideas from the system side, and TSMC and all Tsukuba participants are trying very hard to get it done, of course, with quite some Japanese government money. I guess Apple and AMD should be very satisfied with the current arrangement.

I heard a Japanese official/scholar using the term “US-Japan-Taiwan semiconductor alliances” to describe the whole thing.

Here are some interesting stories about TSMC Kumamoto fab:

1. Salary: The entry-level to work in Kumamoto fab is 280k JPY per month. According to Kumamoto local news, it is very convincing. Local Universities, vocational colleges, and crane schools are now teaching semiconductors.

2. Local supply chain percentage: Japanese official has indicated local supply chain percentage of TSMC Kumamoto fab is above 50%. As time goes by, the number will be much higher. Given their rich history in semiconductors, they know what they are doing with $3.5bn in subsidies.

3. A meeting: After attending the Tsukuba 3D packaging center opening ceremony about one month ago, the TSMC CEO had a long meeting with the Japanese minister of economics. Does it have anything to do with the US-Japan 2nm initiatives? Will see…

 

[Paul2]

Does TSMC have some edge for advanced packaging development over Intel and Samsung because TSMC's customers such as AMD and Apple work with TSMC for advanced packaging?

Their advantage is complete as Samsung doesn't do packaging, and Intel doesn't for anything than own chips, and even with them it's partially-outsourced for non-CPU products I believe.

TSMC was also not in the packaging club until few years ago, when they started offering own packaging. Tough time for OSATs/packagers.

Much smaller foundries often had own packaging, but that's because on small scale the benefit of having everything under one roof was bigger. The economic advantage for the size of TSMC's clients wasn't big enough to forego OSATs/packaging houses.

I believe the market for that has stagnated, and got less competitive, and that's why TSMC decided to start own packaging service.

 

[mgoldsmith1979]

Does TSMC have some edge for advanced packaging development over Intel and Samsung because TSMC's customers such as AMD and Apple work with TSMC for advanced packaging?

My opinion, the difference is not fab to fab, it is fab to OSATs. The wafer-to-wafer or die-to-wafer attach processes require a clean-room environment standard that is higher than what traditional C4-to-substrate attach requirements are, because the particle size relative to the pitch of the attach needs to be maintained for yield (eg: a particle that won't disrupt a 130um pitch C4 attach might definitely impact a 9um HBI attach). So Apple / AMD are using the advanced assembly from TSMC for the 'wafer level' attach points (including InFO, CoWoS, etc), and the fact they get the substrate assembly is nice-to-have. AMD very well could still use an OSAT for final substrate attach of their V-cache stacked CPUs, or for their floating-bridge dGPUs; those are still in the ~55-30 um pitch regime driven by HBM specs, but Apple's M1 Max has a Si bridge at 25um pitch, and the actual V-cache SRAM attach is ~10-12um (slightly looser than the 9um TSMC advertises for SoIC). IMO they cannot get this work done at OSATs because of the cleanroom spec requirements, and there would be immense costs to the OSATs to build that up "preemptively" (meaning, once there is obviously enough market business to support, the OSATs can fund it, but while it is still only 1-2 customers pursuing this tech, the ROI is too low).

 

[VCT]

My opinion, the difference is not fab to fab, it is fab to OSATs. The wafer-to-wafer or die-to-wafer attach processes require a clean-room environment standard that is higher than what traditional C4-to-substrate attach requirements are, because the particle size relative to the pitch of the attach needs to be maintained for yield (eg: a particle that won't disrupt a 130um pitch C4 attach might definitely impact a 9um HBI attach). So Apple / AMD are using the advanced assembly from TSMC for the 'wafer level' attach points (including InFO, CoWoS, etc), and the fact they get the substrate assembly is nice-to-have. AMD very well could still use an OSAT for final substrate attach of their V-cache stacked CPUs, or for their floating-bridge dGPUs; those are still in the ~55-30 um pitch regime driven by HBM specs, but Apple's M1 Max has a Si bridge at 25um pitch, and the actual V-cache SRAM attach is ~10-12um (slightly looser than the 9um TSMC advertises for SoIC). IMO they cannot get this work done at OSATs because of the cleanroom spec requirements, and there would be immense costs to the OSATs to build that up "preemptively" (meaning, once there is obviously enough market business to support, the OSATs can fund it, but while it is still only 1-2 customers pursuing this tech, the ROI is too low).

How about Intel?　Is Intel as competitive as TSMC for advance packaging in the future?

 

[mgoldsmith1979]

How about Intel?　Is Intel as competitive as TSMC for advance packaging in the future?

Intel has shipped products with their EmIB silicon bridge, which has a similar ~50um pitch, and Foveros which is logic-over-logic 3D stacked also using ~50um per their 2020 architecture day disclosures. Roadmap includes Hybrid Bonding, similar to TSMC SoIC, but nothing in-market on that yet, compared to the AMD V-cache. Samsung has also disclosed at VLSI/IEDM etc 2.5D / 2.3D / 3D assembly roadmaps including for Foundry customers, though I believe their focus (for HBI) is around DRAM stacking in support of HBM3 first and foremost.

 

[Daniel Nenni]

Does TSMC have some edge for advanced packaging development over Intel and Samsung because TSMC's customers such as AMD and Apple work with TSMC for advanced packaging?

Yes, TSMC has put a lot of money into packaging and will continue to do so. If I remember correctly 10% of the CAPEX is for packaging. Packaging keeps customers loyal to TSMC and with the importance of multi die packaging it is also a competitive edge. Tom Dillinger is our packaging blogger. We have been briefed on both TSMC and Intel packaging and do not see a clear advantage for either. TSMC has the advantage of wide customer collaboration. Intel has much deeper packaging experience. It will be interesting to see how Intel commercializes their packaging but one thing I can tell you is that a foundry with packaging offerings is much more competitive than one without, absolutely.

 

[hskuo]

Yes, TSMC has put a lot of money into packaging and will continue to do so. If I remember correctly 10% of the CAPEX is for packaging. Packaging keeps customers loyal to TSMC and with the importance of multi die packaging it is also a competitive edge. Tom Dillinger is our packaging blogger. We have been briefed on both TSMC and Intel packaging and do not see a clear advantage for either. TSMC has the advantage of wide customer collaboration. Intel has much deeper packaging experience. It will be interesting to see how Intel commercializes their packaging but one thing I can tell you is that a foundry with packaging offerings is much more competitive than one without, absolutely.

I remembered 10% of tsmc's CapEx is for Package and Mask. But most of it should be in Package.

 

[kychao]

Yes, TSMC has put a lot of money into packaging and will continue to do so. If I remember correctly 10% of the CAPEX is for packaging. Packaging keeps customers loyal to TSMC and with the importance of multi die packaging it is also a competitive edge. Tom Dillinger is our packaging blogger. We have been briefed on both TSMC and Intel packaging and do not see a clear advantage for either. TSMC has the advantage of wide customer collaboration. Intel has much deeper packaging experience. It will be interesting to see how Intel commercializes their packaging but one thing I can tell you is that a foundry with packaging offerings is much more competitive than one without, absolutely.

Yield & good die loss during packaging are very important besides the pitch numbers and other technical electrical or thermal mechanical parameters for beneficial product design or architecture applications - TSMC or its customers may have some claims on the adv. packaging yields.
Adv. packaging yield # is probably far more sensitive than regular Si wafer yield.