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Intel Products Update

Daniel Nenni

Admin
Staff member
Hear Michelle Johnston Holthaus, CEO of Intel Product Group, Christoph Schell, Chief Commercial Officer, and guests talk about the technologies, solutions and opportunities that will shape our shared future.

About Intel:
Intel, the world leader in silicon innovation, develops technologies, products and initiatives to continually advance how people work and live. Founded in 1968 to build semiconductor memory products, Intel introduced the world's first microprocessor in 1971. This decade, our mission is to create and extend computing technology to connect and enrich the lives of every person on Earth.


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I find it ridiculous that they market self driving with 4 xeons. Seems like they don't consider Mobileye as part of Intel anymore.
 
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Also not very high expectations. "The performance of Arrow Lake with the efficiency of Lunar Lake".

Uhh.. that's literally saying it's going to be Arrow Lake-H and nothing better.
You could also do ARL AND LL refresh. Perhaps we will know more in a few months.

I watched the rest of the product presentation..... no real info
 
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Also not very high expectations. "The performance of Arrow Lake with the efficiency of Lunar Lake".

Uhh.. that's literally saying it's going to be Arrow Lake-H and nothing better.
I don't see how that sounds like a bad product? LNL is about as good as it gets from non Apple PC battery life. Scaling lunar lake like efficiency to ARL performance for high TDP skus and bringing LNL battery life to cheaper segments and offering better margins in the segments Intel already put LNL in sounds like a good product. Will it beat that mobile workstation part AMD just launched no. But that is a niche low volume (even by AMDs modest volume standards) part guzzles power like a truck guzzles gas. Most customers don't care about performance. Diferentation is in offering longer battery lives, cooler chasses, and less fan noise. Proof of that lies in Qualcomm in a single year gaining marketshare that took AMD 8 years to gain.
You could also do ARL AND LL refresh. Perhaps we will know more in a few months.
Let's ignore Intel foundry, existing capacity plans with TSMC and Intel foundry for a minute. Why would Intel products choose to sell more expensive to produce chips that are functionally worse? That is objectively bad buisness.
 
I don't see how that sounds like a bad product?
I may be looking at this wrong, but here's how I'm interpreting this as meh:

- Lunar Lake and Arrow Lake are both on N3B

- Lunar Lake and Arrow Lake share the same cores and architecture; which means efficiency is in theory the same*

If Panther Lake is a newer/updated architecture on a 'superior node', why would the efficiency and performance being equal to that pair be 'good' ? Panther Lake should be *more* efficient than either LL or ARL, and/or more performant than LL or ARL. The wording chosen was "The efficiency of LL and the performance of ARL" which tells me it can only outperform LL at higher power than LL, and can't outperform ARL outright.

*There's nothing I know of that makes LL inherently more efficient than ARL other than it's lower frequency (+ implied lower voltages). Arrow Lake could in theory (with same core count and frequencies) achieve the same efficiency as LL. There are 'noise' differences such as NPU choices, iGPU choices, and cache differences but I am discounting those here.
 
Let's ignore Intel foundry, existing capacity plans with TSMC and Intel foundry for a minute. Why would Intel products choose to sell more expensive to produce chips that are functionally worse? That is objectively bad buisness.
I dont know the cost for panther lake but it is not obvious to me it is cheaper while 18A is ramping. If you know it is cheaper unit cost than LL and ARL then Intel margins will go up and costs go down when 18A ramps.

the bigger issue might be finance



I lease my office because I cannot afford to buy an office building..... I also dont need the volume of office. Even though it would be theoretically cheaper to buy an office building ("margin stacking").

If I bought an office building I would be complaining how I lose money because the offices are not full, there is a bunch of development expenses, depreciation is killing me .... but by 2027 or 2030 my office building will be making money.

Meanwhile people are renting nicer, lower power offices from the famous building owner across the street and my business doesnt pick up as I had hoped.

Unless China invades the office across the street, then I am rich :LOL: :ROFLMAO: :LOL: :ROFLMAO:
 
I don't see how that sounds like a bad product? LNL is about as good as it gets from non Apple PC battery life. Scaling lunar lake like efficiency to ARL performance for high TDP skus and bringing LNL battery life to cheaper segments and offering better margins in the segments Intel already put LNL in sounds like a good product. Will it beat that mobile workstation part AMD just launched no. But that is a niche low volume (even by AMDs modest volume standards) part guzzles power like a truck guzzles gas. Most customers don't care about performance. Diferentation is in offering longer battery lives, cooler chasses, and less fan noise. Proof of that lies in Qualcomm in a single year gaining marketshare that took AMD 8 years to gain.

Let's ignore Intel foundry, existing capacity plans with TSMC and Intel foundry for a minute. Why would Intel products choose to sell more expensive to produce chips that are functionally worse? That is objectively bad buisness.
They mentioned a story using AI PC for military applications. I assume low power is very important.
 
They also demoed kamiwaza.ai on a Gaudi 3 node (8x accelerators) for weather data retrieval and processing. I think that is quite interesting.

If I would consider providing services like that, I think Intel Gaudi is a compelling option.
 
I may be looking at this wrong, but here's how I'm interpreting this as meh:

- Lunar Lake and Arrow Lake are both on N3B

- Lunar Lake and Arrow Lake share the same cores and architecture; which means efficiency is in theory the same*

If Panther Lake is a newer/updated architecture on a 'superior node', why would the efficiency and performance being equal to that pair be 'good' ? Panther Lake should be *more* efficient than either LL or ARL, and/or more performant than LL or ARL. The wording chosen was "The efficiency of LL and the performance of ARL" which tells me it can only outperform LL at higher power than LL, and can't outperform ARL outright.

*There's nothing I know of that makes LL inherently more efficient than ARL other than it's lower frequency (+ implied lower voltages). Arrow Lake could in theory (with same core count and frequencies) achieve the same efficiency as LL. There are 'noise' differences such as NPU choices, iGPU choices, and cache differences but I am discounting those here.
LNL is hilariously more efficient than ARL in the intended scenarios for LNL:
  • On package memory
  • IMC on compute die
  • Fewer D2D power losses
  • Higher percentage of total Si area using the most advanced process
  • Better NPU and GPU IPs are more efficient
  • Smaller GPU (more power efficient)
  • GPU, NPU, LP e core cluster on same die with CPU
  • SOC cache
  • Better power delivery and regulators
  • Finally phasing out Intel's outdated race to idle power management scheme for a more mobile like rapid switching between various power states to minimize power consumption across the workload rather than after the work was done

As for Pantherlake only being similar to LNL on battery life. There are choices that Intel communicated, or are wildly known or believed to be true that would blur some of the improvements you would expect from say a 2nm LNL:
  • Intel every quarter talks about how no on package memory saves a ton of cash and lifts margins
  • PNL has more dies increasing power consumption
  • It is unclear if PNL has SOC cache still
  • Core IP is a die shrink so it isn't meaningfully better if you take away the extra 18A process entitlment
  • Rumored to have a bigger GPU than LNL
  • This is first year of production 18A vs second year of production N3 so N3 variation should be lower (reducing some of the power advantages 18A intrinsically has)
  • The whole chip isn't 18A so the 18A benefits only apply to the 18A components
  • Since this wasn't intended to be an ultra premium MacBook air compete chip it likely won't have those fancy PMICs
  • PNL has a higher performance target than LNL so not all of the power savings are being passed towards lowering power consumption
  • It is unknown if PNL is race to idle or not, but if it is whoever made that call needs to be fired ASAP. So I would tentatively say it should have that
  • While 18A is pretty close to N2, N3 is also pretty close to N2. So it isn't like N3 to 18A was ever going to be some giant leap (like say going from T40nm to T28nm)
I dont know the cost for panther lake but it is not obvious to me it is cheaper while 18A is ramping.
To Intel products it doesn't matter if utilization is 1%. They pay a fixed price and MJ says it is cheaper and higher margin than current products. Especially LNL which is already being sold into cheaper laptops than expected because ARL U (and no I don't mean MTL on Intel 3) was that bad and nobody wanted it. Pictures also seems like die area has walked away from the near 300mm2 of ARL and more than 250mm2 MTL. If the biggest PNL die for the biggest sku is around 140, then whole chips is definitely smaller than MTL.

As for foundry: clearly ramp it isn't unbearably painful since this is the peak of foundry losses (all the cost plus no revenue until EOY), and Intel has continued to stick with the story of 27 break even and rapid operating loss reduction in 2026.
If you know it is cheaper unit cost than LL and ARL then Intel margins will go up and costs go down when 18A ramps.
I mean yeah. How could it not? It is a fact Intel 7 is sold near cost, and Intel says the 18A ASP is 3x while wafer cost is not up meaningfully. 2+2=4 and 18A margin is greatly improved. If 18A margins weren't at least ok, break even would have never been possible in 2027. Let's be bearish and say single digit Intel 7 margin means 1%. Cost = 1 and price = 1.01. Even if we say Intel is lying and 18A cost isn't modestly higher, but is really 2x i7. Okay P=3.03 and C=2. GM is 34% (lower than what TSMC makes on these new nodes but similar to what UMC or GF do in fully deprecated fabs). Even if we say i7 GM is -9% (P=1 and C=1.09), 18A margin comes out as 27% with all other assumptions being the same (3x price and 2x cost).

edit: fixed the math for the 1% margin case. I had a brain fart and used the wrong number and got a 39% margin rather than a 34%.

As a side note the statement of 18A cost not being much higher than i7 and being similar to N2 means that Intel 7 cost is somewhere around N3 cost of production. Considering a lot of those N3 layers are more expensive EUV layers, that would indicate that i7 probably has wildly more mask layers than even N2 if cost is similar to N3. Which is insane but not exactly shocking when you look at a teardown. It certainly explains why for all of the Intel 7 volume there is no profit after you take out R&D, ecosystem building, and building more than 1 EUV capable fab outside of Oregon. One can certainly see why Intel is very jazzed to be moving past i7.
 
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As a side note the statement of 18A cost not being much higher than i7 and being similar to N2 means that Intel 7 cost is somewhere around N3 cost of production. Considering a lot of those N3 layers are more expensive EUV layers, that would indicate that i7 probably has wildly more mask layers than even N2 if cost is similar to N3. Which is insane but not exactly shocking when you look at a teardown. It certainly explains why for all of the Intel 7 volume there is no profit after you take out R&D, ecosystem building, and building more than 1 EUV capable fab outside of Oregon. One can certainly see why Intel is very jazzed to be moving past i7.

Interesting point. The first version of N3 had more EUV layers than it does today. I don't remember the actual count but it was a significant reduction. Does anyone know how many EUV layers there are for N3 and N2? Does GAA require more than FinFET?
 
Interesting point. The first version of N3 had more EUV layers than it does today. I don't remember the actual count but it was a significant reduction.
That wasn't the main cost savings. The biggest cost savings and long term yield enhancement from N3 -> N3E is getting rid of that Self Aligned Gate End Cap and moving from self-aligned contracts to direct print contacts. Things like moving M1P from 3:2 CPP gear ratio to 1:1 and using direct print EUV are comparatively minor cost savings.
Does GAA require more than FinFET?
Yes, by nature, GAA requires direct print of things like nanosheets to accommodate flexible device widths. Meanwhile, with finFET it is just easier to use spacer based pitch quartering for fin definition and cut wherever you want since every fin is uniform in size. Wouldn't surprise me if there were more applications where EUV is used on N2 where it wasn't on N3 or N3E, but that is the one that comes to mind right away.
 
LNL is hilariously more efficient than ARL in the intended scenarios for LNL:
  • On package memory
  • IMC on compute die
  • Fewer D2D power losses
  • Higher percentage of total Si area using the most advanced process
  • Better NPU and GPU IPs are more efficient
  • Smaller GPU (more power efficient)
  • GPU, NPU, LP e core cluster on same die with CPU
  • SOC cache
  • Better power delivery and regulators
  • Finally phasing out Intel's outdated race to idle power management scheme for a more mobile like rapid switching between various power states to minimize power consumption across the workload rather than after the work was done

As for Pantherlake only being similar to LNL on battery life. There are choices that Intel communicated, or are wildly known or believed to be true that would blur some of the improvements you would expect from say a 2nm LNL:
  • Intel every quarter talks about how no on package memory saves a ton of cash and lifts margins
  • PNL has more dies increasing power consumption
  • It is unclear if PNL has SOC cache still
  • Core IP is a die shrink so it isn't meaningfully better if you take away the extra 18A process entitlment
  • Rumored to have a bigger GPU than LNL
  • This is first year of production 18A vs second year of production N3 so N3 variation should be lower (reducing some of the power advantages 18A intrinsically has)
  • The whole chip isn't 18A so the 18A benefits only apply to the 18A components
  • Since this wasn't intended to be an ultra premium MacBook air compete chip it likely won't have those fancy PMICs
  • PNL has a higher performance target than LNL so not all of the power savings are being passed towards lowering power consumption
  • It is unknown if PNL is race to idle or not, but if it is whoever made that call needs to be fired ASAP. So I would tentatively say it should have that
  • While 18A is pretty close to N2, N3 is also pretty close to N2. So it isn't like N3 to 18A was ever going to be some giant leap (like say going from T40nm to T28nm)

To Intel products it doesn't matter if utilization is 1%. They pay a fixed price and MJ says it is cheaper and higher margin than current products. Especially LNL which is already being sold into cheaper laptops than expected because ARL U (and no I don't mean MTL on Intel 3) was that bad and nobody wanted it. Pictures also seems like die area has walked away from the near 300mm2 of ARL and more than 250mm2 MTL. If the biggest PNL die for the biggest sku is around 140, then whole chips is definitely smaller than MTL.

As for foundry: clearly ramp it isn't unbearably painful since this is the peak of foundry losses (all the cost plus no revenue until EOY), and Intel has continued to stick with the story of 27 break even and rapid operating loss reduction in 2026.

I mean yeah. How could it not? It is a fact Intel 7 is sold near cost, and Intel says the 18A ASP is 3x while wafer cost is not up meaningfully. 2+2=4 and 18A margin is greatly improved. If 18A margins weren't at least ok, break even would have never been possible in 2027. Let's be bearish and say single digit Intel 7 margin means 1%. Cost = 1 and price = 1.01. Even if we say Intel is lying and 18A cost isn't modestly higher, but is really 2x i7. Okay P=3.03 and C=2. GM is 34% (lower than what TSMC makes on these new nodes but similar to what UMC or GF do in fully deprecated fabs). Even if we say i7 GM is -9% (P=1 and C=1.09), 18A margin comes out as 27% with all other assumptions being the same (3x price and 2x cost).

edit: fixed the math for the 1% margin case. I had a brain fart and used the wrong number and got a 39% margin rather than a 34%.

As a side note the statement of 18A cost not being much higher than i7 and being similar to N2 means that Intel 7 cost is somewhere around N3 cost of production. Considering a lot of those N3 layers are more expensive EUV layers, that would indicate that i7 probably has wildly more mask layers than even N2 if cost is similar to N3. Which is insane but not exactly shocking when you look at a teardown. It certainly explains why for all of the Intel 7 volume there is no profit after you take out R&D, ecosystem building, and building more than 1 EUV capable fab outside of Oregon. One can certainly see why Intel is very jazzed to be moving past i7.
I was going to answer xebec's post, but with your excellent response there's no need. I would mention, however, that the PC OEMs are known to despise the integrated DRAM dies. Given the power savings and latency improvements from integration, I think less of them than I did before. Difficult to imagine, since every time my wife gets a new Dell or ThinkPad and I have to deal with their [expletive deleted] bloatware.
 
I may be looking at this wrong, but here's how I'm interpreting this as meh:

- Lunar Lake and Arrow Lake are both on N3B

- Lunar Lake and Arrow Lake share the same cores and architecture; which means efficiency is in theory the same*

If Panther Lake is a newer/updated architecture on a 'superior node', why would the efficiency and performance being equal to that pair be 'good' ? Panther Lake should be *more* efficient than either LL or ARL, and/or more performant than LL or ARL. The wording chosen was "The efficiency of LL and the performance of ARL" which tells me it can only outperform LL at higher power than LL, and can't outperform ARL outright.

*There's nothing I know of that makes LL inherently more efficient than ARL other than it's lower frequency (+ implied lower voltages). Arrow Lake could in theory (with same core count and frequencies) achieve the same efficiency as LL. There are 'noise' differences such as NPU choices, iGPU choices, and cache differences but I am discounting those here.
There is LNL Power delivery mechanism it uses PMIC rather than traditional VRM and their improved L3/NOC ARL has a 80 Cycle L3 while LNL has 55 Cycle L3 not to mention a system Level Cache .The iGPU is better in terms of HW/Architecture Xe2 vs Xe1+ in ARL-H improved media engines . Their is everything in LnL that screams low Power.

It can be translated as it can achieve ARL-H level Performance at LNL power budget btw the architecture in Panther Lake is using is Cougar Cove and Darkmont both are refreshes with minor improvements and +5-7% IPC improvement what Intel used to call a Tick.
 
I was going to answer xebec's post, but with your excellent response there's no need. I would mention, however, that the PC OEMs are known to despise the integrated DRAM dies. Given the power savings and latency improvements from integration, I think less of them than I did before. Difficult to imagine, since every time my wife gets a new Dell or ThinkPad and I have to deal with their [expletive deleted] bloatware.
It's not just dell/Lenovo every vendor does this except for framework they don't even have windows installed.

Also this presentation was horrible I would give negative points and say they have wasted people's time and their 💰.
 
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I find it ridiculous that they market self driving with 4 xeons. Seems like they don't consider Mobileye as part of Intel anymore.
Zoox, now an Amazon company, picked the silicon, not Intel. Though Zoox's CEO Aicha Evans was a former Intel executive, I suspect the architecture was far along before she joined.
 
That wasn't the main cost savings. The biggest cost savings and long term yield enhancement from N3 -> N3E is getting rid of that Self Aligned Gate End Cap and moving from self-aligned contracts to direct print contacts. Things like moving M1P from 3:2 CPP gear ratio to 1:1 and using direct print EUV are comparatively minor cost savings.
I had the impression the main changes were EUV reduction and pitch relaxation.
Yes, by nature, GAA requires direct print of things like nanosheets to accommodate flexible device widths. Meanwhile, with finFET it is just easier to use spacer based pitch quartering for fin definition and cut wherever you want since every fin is uniform in size. Wouldn't surprise me if there were more applications where EUV is used on N2 where it wasn't on N3 or N3E, but that is the one that comes to mind right away.
The nanosheet pitch design rules should be roughly half the smallest cell height ~65 nm, it should be comparable to N16 MMP.
 
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