5nm becoming the non-EUV leading edge

[Fred Chen]

The eBeam Initiative’s 12th annual Luminaries survey in 2023 reported a range of nodes from >5nm to 14nm as the most advanced non-EUV nodes using 193i lithography. For the 2030 timeline, 5nm or less picked up more support.

In the discussion summarized here https://semiengineering.com/industr...ities-for-advancing-the-non-euv-leading-edge/, panelists cited several factors driving 193i down to smaller nodes starting with the high cost of EUV, the potential of curvilinear 193i masks to replace one or more EUV layers, and the availability of multi-beam mask writers and new laser writers that can write curvilinear 193i masks.

There was a particularly interesting statement from Chris Progler (CTO of Photronics):
We see the opportunity to extend 193i to a couple more layers to make a better chip, even below 7nm. We have several customers saying “if I can get this one layer to look like 5nm using 193i, it carries along the performance for a lot of the other functionality.”

 

[MKWVentures]

The eBeam Initiative’s 12th annual Luminaries survey in 2023 reported a range of nodes from >5nm to 14nm as the most advanced non-EUV nodes using 193i lithography. For the 2030 timeline, 5nm or less picked up more support.

In the discussion summarized here https://semiengineering.com/industr...ities-for-advancing-the-non-euv-leading-edge/, panelists cited several factors driving 193i down to smaller nodes starting with the high cost of EUV, the potential of curvilinear 193i masks to replace one or more EUV layers, and the availability of multi-beam mask writers and new laser writers that can write curvilinear 193i masks.

There was a particularly interesting statement from Chris Progler (CTO of Photronics):
We see the opportunity to extend 193i to a couple more layers to make a better chip, even below 7nm. We have several customers saying “if I can get this one layer to look like 5nm using 193i, it carries along the performance for a lot of the other functionality.”

so what is the smallest pitch or line on this "5nm" process?

 

[Fred Chen]

so what is the smallest pitch or line on this "5nm" process?

I think it may be closer to Samsung's "5nm". Samsung participates as a member in these eBeam initiative surveys. Not sure TSMC is involved so much.

 

[nghanayem]

Very interesting find Fred thanks for sharing.

so what is the smallest pitch or line on this "5nm" process?

My read of this article was talking about moving layers that were kind of borderline EUV to some computational litho/curvilinear wizardry DUV, LELELE, SALELE or SAPD scheme. I doubt TSMC could ever make N5 fully DUV (at least in an economical high yielding way that is easy to design for). Doubly so because they already payed for their EUV tools in those fabs. However it is totally plausible to maybe be able to do gate patterning, M4, or something like that with a cheaper litho scheme that lowers the NRE and wafer costs enough to have some N7 products move over to N5. I would be more excited to see how this works for 16FF/14LPP. If memory serves those nodes uses LELE for M0, but only barely. If you could move most of the LELE layers to direct print, well hot dog 16FF/14LPP would now have wafer costs similar to 28nm.

I think it may be closer to Samsung's "5nm". Samsung participates as a member in these eBeam initiative surveys. Not sure TSMC is involved so much.

If you were to do a 5"nm" process with DUV without going to some crazy SALELELE or SAQP scheme yeah it would just have to be Samsung like or my guess even a bit more relaxed to like 38nm instead of the 36nm min metal pitch of 5LPE.

 

[Fred Chen]

For 36 nm pitch, LELE cut may be ok, though LELELE would have almost no restrictions https://www.spiedigitallibrary.org/...s-for-sub-20nm-metal/10.1117/12.2085716.short