Cloud-enabled Workshop on “RISC-V based SoC design”
Good news is – Anyone from any part of the world at any time-zones can join. It is open 24hrs between 27th May to 31st May. So, you can enter and exit whenever you are comfortable
$25
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3 events,
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CHIPKIT: 2nd Tutorial on Agile Research Test Chips @ISCA’20
CHIPKIT: 2nd Tutorial on Agile Research Test Chips @ISCA’20
Paul Whatmough (Arm Research/Harvard), Marco Donato (Harvard), Glenn Ko (Harvard), Sae-Kyu Lee (IBM Research), David Brooks (Harvard), and Gu-Yeon Wei (Harvard) Updates CHIPKIT @ISCA’20 31st May 2020, 10am-1pm EDT - Live Q&A session. Pre-recorded videos available during the conference via the Whova app. Register for tutorial Overview Research test chips are the ultimate experiment to demonstrate the true value of novel computer architecture innovations. They are …
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Webinar: Investigating and Improving Clock Delays
Webinar: Investigating and Improving Clock Delays
Overview As typical system-on-chip designs grow larger and move to the latest FinFET process nodes, clocking constraints become ever more complex. The Cadence® Innovus™ Implementation System’s CCOpt™ useful skew optimization engine is a powerful tool to close the timing on the latest high-speed designs. Understanding and managing insertion delay is an important part of clock …
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9 events,
COMPUTEX
About COMPUTEX Established in 1981, COMPUTEX TAIPEI (also called COMPUTEX) is the leading global ICT and IoT show with a complete supply chain and ecosystems. Co-organized by the Taiwan External Trade Development Council (TAITRA) and Taipei Computer Association (TCA), COMPUTEX, based upon Taiwan’s complete ICT clusters, covers the whole spectrum of ICT industry, from established …
CEVA Technology Virtual Seminar 2020 – Spring Edition – Communication
June 2, 2020 5G and Wi-Fi 6 solutions for User Equipment, Automotive, Small Cells, and Access Points Register Now
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Better UVM Debug with Visualizer
Better UVM Debug with Visualizer
Register For This Web Seminar Online - Jun 2, 2020 8:00 AM - 9:00 AM US/Pacific Register Overview Intuitive and easy to use, Visualizer Debug Environment automates debugging for the digital design and verification of today's complex SoCs and FPGAs. Find problems in your UVM testbench faster using Visualizer Debug Environment, a high-performance, high-capacity debugger. …
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WEBINAR: eFPGA what’s available now, what’s coming & what’s possible to optimize your SoC
WEBINAR: eFPGA what’s available now, what’s coming & what’s possible to optimize your SoC
Learn why eFPGA adoption is taking off. eFPGA is now widely available; has been used in dozens of chips and is being designed into dozens more; and has an increasing list of benefits for a range of applications. Embedded FPGA, or eFPGA, enables your SoC to have flexibility in critical areas where algorithm, protocol or …
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Learn Criticality and Sustainability of Materials With the SusCritMat Project
Learn Criticality and Sustainability of Materials With the SusCritMat Project
June 2, 2020 11 AM EDT / 3 PM GMT Venue: Online SusCritMat is a European Institute of Innovation & Technology (EIT) RawMaterials funded education project which develops teaching modules on critical raw materials and their sustainable management, taking into account the different perspectives as well as the entire value chain. This webinar will present …
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Webinar: Conformal 2020 Updates to Improve Productivity and Silicon Success
Webinar: Conformal 2020 Updates to Improve Productivity and Silicon Success
Overview As designs grow in complexity, rigorous formal verification is essential to meet aggressive requirements for power, performance, area, and time to market. Equivalence checking, static verification, automated ECO, and constraint design for clock domain crossing (CDC) are some of the challenges that signoff designers have to consider. Join this quarterly webinar on Cadence® Conformal® …
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Enhance Your Knowledge: Tips and Tricks for CFD Meshing
Enhance Your Knowledge: Tips and Tricks for CFD Meshing
June 2, 2020 11:30 AM (IST) Venue: Online Accuracy and solution time are two of the most critical concerns in computational fluid dynamics (CFD) simulation, and both greatly depend on the characteristics of the mesh. Different types of meshing elements are needed to deliver optimal performance in resolving unique geometries and flow regimes. Ansys is …
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9 events,
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Moving to Linux
Moving to Linux
Register For This Web Seminar Online - Jun 4, 2020 9:00 AM - 10:00 AM US/Pacific Register Overview There many things to considers when moving to Linux for embedded projects. Based on pragmatic experience of helping customers through the decision-making process and the actual transition, this webinar provides practical information, so developers can be fully …
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Chemistry Tools for Electronics Failure Analysis
Chemistry Tools for Electronics Failure Analysis
Thu, Jun 4, 2020 9:00 AM - 10:00 AM MDT Many analytical chemistry techniques can aid in electronic failure analysis. Analytical chemistry techniques collect atomic or molecular information from samples, which help identify contamination or materials used. Key concepts discussed in this webinar include the exact chemical information each technique collects, the risks of an …
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TRAINING: DESIGNING MMWAVE MIMO RADAR SYSTEMS WITH AWR SOFTWARE
TRAINING: DESIGNING MMWAVE MIMO RADAR SYSTEMS WITH AWR SOFTWARE
Date/Time: Thursday, June 4 10:00am PDT Presenter: Dr. Tero Kiuru, VTT This web presentation covers the design of a frequency-modulated continuous wave (FMCW) MIMO radar system with Cadence® AWR Design Environment® software. The purpose of the system is for short-range high-resolution localization of nearby moving objects. Four-channel transmitter and receiver chips are designed using a 130nm SiGe process. …
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Introducing Ansys RaptorH: SoC, Mixed-Signal and RFIC Electromagnetic Modeling
Introducing Ansys RaptorH: SoC, Mixed-Signal and RFIC Electromagnetic Modeling
June 4, 2020 10:30 AM (EDT) Venue: Online Ansys RaptorH adds to Ansys’ comprehensive set of electromagnetic (EM) field solver modeling capabilities, which extend from devices to chips to full electronics systems. The enhanced on-silicon EM simulation now includes the Ansys HFSS gold-standard engine integrated into an easy-to-use interface for chip designers, while maintaining the …
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Modeling Hydraulic Systems With Ansys Twin Builder
Modeling Hydraulic Systems With Ansys Twin Builder
June 4, 2020 11 AM (EDT) /3 PM (GMT) Venue: Online Hydraulic systems must perform as designed, especially in safety-critical applications. Ansys Twin Builder can help you easily and more efficiently design hydraulic systems that will operate as expected, and reduce your design efforts and time to market. This webinar covers the modeling of hydraulic …
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3 events,
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Taking SystemVerilog Arrays to the Next Dimension
Taking SystemVerilog Arrays to the Next Dimension
Register For This Web Seminar Online - Jun 5, 2020 8:15 AM - 8:45 AM US/Pacific Register Overview Chris Spear, Principle Instructor, presents a detailed description of the various array types in the SystemVerilog language, and how to pick the right ones for your testbench. SystemVerilog has many dynamic data types, and you will learn …
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Ansys Fluent 2020: Updated user-Environment, streamlined workflows, improved meshing and great new solver functionality for a more productive CFD experience
Ansys Fluent 2020: Updated user-Environment, streamlined workflows, improved meshing and great new solver functionality for a more productive CFD experience
June 5, 2020 11.00 am (BST) Venue: Online Contact: uk-marketing@ansys.com 0114 281 8888 Ansys Fluent is Ansys' flagship product for multi-purpose CFD simulation and is famed for its advanced physics, solver accuracy and wide-ranging applicability to many different fluid flow applications. The 2020 release of Ansys Fluent brings further advances in solver functionality. Hundreds of …
6 events,
LiveWorx
LIVEWORX 2020 IS GOING VIRTUAL! In light of the global coronavirus (COVID-19) pandemic, we have decided to reimagine LiveWorx 2020 as a complimentary virtual event. As we work through the details of this digital experience, we will continue to share updates here. Sign-up to receive real-time notifications. VIRTUAL EVENT: JUNE 9, 2020 THE DEFINITIVE EVENT FOR …
SID DISPLAY WEEK 2020
2020 PROGRAM The Society for Information Display's annual Display Week runs from June 7th - June 12th, offering a wide selection of display technology presentations by global experts that simply cannot be found anywhere else. SID International Symposium The four-day Symposium features hundreds of leading display industry papers from around the world in multiple technical sessions. It …
CEVA Technology Virtual Seminar 2020 – Spring Edition – AI and Vision
June 9, 2020 AI processing for neural network-based applications and computer vision for camera-enabled devices in smartphones, wearables, ADAS and surveillance Register now
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WEBINAR: ESD Protection Network Verification Using Magwel’s ESDi for HBM Simulation
WEBINAR: ESD Protection Network Verification Using Magwel’s ESDi for HBM Simulation
Verifying the Electrostatic Discharge (ESD) protection network on an IC can be challenging, and if it is not done correctly it can lead to failures on the tester, reduced product reliability or shortened field life. In this webinar you will learn how Magwel’s ESDi thoroughly analyzes all pad combinations in a design for comprehensive ESD …
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Tessent Safety – Entering the Safety Ecosystem: a reference flow for automotive IC test
Tessent Safety – Entering the Safety Ecosystem: a reference flow for automotive IC test
Register For This Web Seminar Online - Jun 9, 2020 5:00 PM - 6:00 PM US/Pacific Register Online - Jun 10, 2020 8:00 AM - 9:00 AM US/Pacific Register Overview Industry-leading innovations in automotive electronics has immensely contributed in the development of advanced safety mechanism resulting in exponential growth in the amount of electronics that …
7 events,
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Faster, Real-time & Interactive Cable & Wiring Harness Documentation Webinar
Faster, Real-time & Interactive Cable & Wiring Harness Documentation Webinar
Overview: Join this webinar to learn a faster method to automatically create cable and wire harness documentation for the automotive & aerospace industry to reduce errors and costs in development, manufacture and maintenance. This is crucial in today’s complex systems with configuration variability and constant design changes compared to today’s static PDF manuals. Beat the time …
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FREE
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A Key Principle to Successful Tapeouts for Cadence Virtuoso Users Webinar
A Key Principle to Successful Tapeouts for Cadence Virtuoso Users Webinar
Overview: Having difficulties in keeping track of changes to schematics and layouts in Cadence Virtuoso? In this webinar we will show you a methodology that engineers have been adopting to reduce inefficiencies and become more productive and increase throughput. Sign up for this webinar here What you will learn: Revision control with release and …
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FREE
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Introducing ODB++Process
Introducing ODB++Process
Register For This Web Seminar Online - Jun 11, 2020 11:00 AM - 12:00 PM Etc/GMT+3 Register Overview Siemens introduces its newest data exchange format for electronic manufacturing equipment vendors, ODB++Process (formally known as OPM). ODB++Process (ODB++P) enables the exchange of intelligent assembly process engineering data between Valor Process Preparation (the advanced programming solution powered by Valor …
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Questa Clock/Reset Domain Crossing Verification / Mentor Functional Safety Compliance – What’s New in Functional Verification from Mentor: Session 5
Questa Clock/Reset Domain Crossing Verification / Mentor Functional Safety Compliance – What’s New in Functional Verification from Mentor: Session 5
Register For This Web Seminar Online - Jun 11, 2020 4:00 PM - 5:00 PM Europe/London Register Online - Jun 11, 2020 4:00 PM - 5:00 PM US/Pacific Register This is the fifth of a 5-part series on “What’s New in Functional Verification from Mentor.” Each session will be presented twice at the times shown above consisting of two …
14 events,
CAASE20: Conference on Advancing Analysis & Simulation in Engineering | Presented by NAFEMS and Digital Engineering
Important Message to CAASE20 Participants (Published on March 26th, 2020) Over the past several weeks, NAFEMS and Digital Engineering Magazine have explored numerous scenarios and options with the safety and best interests of our community in mind. We came to the decision to bring CAASE20 “online.” Many of us are dealing with a significant amount of uncertainty …
2020 Symposia on VLSI Technology and Circuits
VLSI 2020 is going virtual! Given the global health concerns associated with COVID-19 (Coronavirus), the organization of VLSI 2020 has decided to hold the 2020 VLSI Symposia on Technology and Circuits as a virtual conference. Although we will not be meeting in Honolulu this year and it will be impossible to reproduce the lively discussions …
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Introduction to Visualizer for the Verilog Users
Introduction to Visualizer for the Verilog Users
Register For This Web Seminar Online - Jun 16, 2020 8:00 AM - 9:00 AM US/Pacific Register Overview Complex testing and methodology with complex silicon require powerful but simple to use debug solutions. The Visualizer Debug Environment provides a common debug solution for simulation, emulation and other engines, including Verilog, VHDL, UVM, SystemC, C/C++, Assertions …
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Accelerate Aerospace & Defence Technology Innovation with Ansys Tools
Accelerate Aerospace & Defence Technology Innovation with Ansys Tools
RESCHEDULED Accelerate Aerospace & Defence Technology Innovation with Ansys Tools June 16, 2020 9:00 - 17:00 (CET) Venue: O.C. Hotel Via Tiburtina, 1352 00131 Roma Italy Contact: Marketing Italia info.italia@ansys.com Facing an increasingly competitive, threat-filled environment, aerospace and defense companies must digitally transform to deliver radical innovation. ANSYS multidisciplinary simulation solutions create the digital thread, …
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Free Webinar on efficiently tracking KPIs across multiple factories using LineWorks SPACE and STARGATE
Free Webinar on efficiently tracking KPIs across multiple factories using LineWorks SPACE and STARGATE
Stargazing quality KPIs across your factories This webinar will occur twice on the following dates: Tue, June 16, 2020 9:00 AM - 10:00 AM PDT GMT-7 (Suitable for attendees from USA and Europe) Thu, June 18, 2020 3:00 PM - 4:00 PM GMT+8 (Suitable for attendees from Europe and Asia) Please register for the date and time that works best for you. Register now! Come join our webinar and learn how to … Use LineWorks SPACE to automate and …
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Accelerate Aerospace & Defence Technology Innovation with Ansys Tools
Accelerate Aerospace & Defence Technology Innovation with Ansys Tools
June 16, 2020 9:00 - 17:00 (CET) Venue: O.C. Hotel Via Tiburtina, 1352 00131 Roma Italy Contact: Marketing Italia info.italia@ansys.com Facing an increasingly competitive, threat-filled environment, aerospace and defense companies must digitally transform to deliver radical innovation. Ansys multidisciplinary simulation solutions create the digital thread, which supports the flow of data throughout the product life …
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WEBINAR: Securing Your SoCs: Advanced Techniques for Security Verification
WEBINAR: Securing Your SoCs: Advanced Techniques for Security Verification
Security concerns permeate our digital lives. From online financial or personal data transactions, to automobile control and even election tampering, protecting access has become a critical necessity for almost all applications. With semiconductor hardware forming the foundation of modern electronic systems, a hack here can be disastrous. Protecting hardware against the myriad of potential vulnerabilities …
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10 events,
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Combining Parametric Modeling with Design Exploration
Combining Parametric Modeling with Design Exploration
June 18, 2020 10 AM (EDT) / 2 PM (GMT) Venue: Online Computer-aided engineering (CAE) helps investigate large numbers of product variants across numerous product application scenarios. This is a key strategy to cut costs and shorten design cycles during the virtual product development process. Ansys has a long history in supporting this process using …
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WEBINAR: ADVANCED POWER AMPLIFIER DESIGN WITH AWR SOFTWARE
WEBINAR: ADVANCED POWER AMPLIFIER DESIGN WITH AWR SOFTWARE
Webinar Details Advanced Power Amplifier Design with AWR Software Date: Thursday, June 18, 2020 Time: 10:00am PDT Questions about this event? Send email to: events@cadence.com This webinar showcases the advanced load pull-based design flows for high-power amplifiers (HPAs) within the Cadence® AWR Design Environment® platform. Load pull has become an integral tool for PA designers needing to meet aggressive performance …
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AI Requires Tailored DRAM Solutions
AI Requires Tailored DRAM Solutions
June 18th at 11am PT | 2pm ET Join Rambus for a webinar exploring how Dynamic Random Access Memory (DRAM) is a key enabler for Artificial Intelligence (AI). Featuring Frank Ferro, senior director of product management for memory interface IP at Rambus, and Shane Rau, research vice president, computing semiconductors at IDC, this webinar will …
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Electronics Design for Manufacturability (DfM): Avoiding Failure After Reflow
Electronics Design for Manufacturability (DfM): Avoiding Failure After Reflow
June 18, 2020 11:00 AM (EDT) Venue: Online In the electronics industry, the capability of manufacturing suppliers greatly impacts the quality and reliability of any product. Manufacturing issues are one of the top reasons that companies fail to meet warranty expectations. Both process and design can play critical roles during manufacturing, while design for manufacturability …
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Modern Day Methods Demonstrated on Classic Forms
Modern Day Methods Demonstrated on Classic Forms
June 18, 2020 11:00 AM (EDT) Venue: Online For years engineers have enjoyed the relative ease of connecting their CAD geometry with their analysis tools. But what do you do when a CAD model of your structure does not exist? How do you take data from a scan and use it in a finite element …
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11 events,
How Ansys Simulation Enables Cutting Edge Wind Technology Development
Overview Wind energy is considered an important part of the global renewable energy strategy. Therefore, it is imperative that the development of these technologies matches the speed at which they are needed. Join Ansys and our customers as we explore how a simulation led approach enables the rapid development of their products in an industrial …
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Webinar: How Row-Based Methodology Improves Custom Layout
Overview Want to do more projects with the same number of people? Keep the same schedule timelines as previous nodes? Allow for more deterministic layout quality and schedule? Reduce design time? At advanced nodes, the complexity and volume of design rules have been growing exponentially. Newer process technologies at 10nm and below require fully colored …
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WEBINAR: COMPREHENSIVE RTL SIGNOFF BY DESIGNERS USING JASPERGOLD SUPERLINT
WEBINAR: COMPREHENSIVE RTL SIGNOFF BY DESIGNERS USING JASPERGOLD SUPERLINT
Webinar Details Comprehensive RTL Signoff by Designers Using JasperGold Superlint Date: Wednesday, June 24, 2020 Time: 08:00 PDT / 17:00 CEST / 18:00 IDT / 20:30 IST Questions about this event? Send email to: eur_training@cadence.com You can’t afford to go through weeks of verification only to discover problems in the register-transfer level (RTL) code—problems which may lead to …
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Optimizing Hardware Layout Designs
Optimizing Hardware Layout Designs
June 24, 2020 11 AM EDT / 3 PM GMT Venue: Online This webinar showcases how a leading-edge hardware design process bridges the challenging gaps that occur between analysis and layout design. We will examine typical discrepancies that range from translating geometry between layout and simulation environments to communicating changes from the analysis back to …
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Tips and Tricks for Optimizing Your Development and Reducing Your FEA Preprocessing Time
Tips and Tricks for Optimizing Your Development and Reducing Your FEA Preprocessing Time
June 24, 2020 11:30 AM (IST) Venue: Online Ansys Mechanical users continue to solve highly complex engineering problems faster and more efficiently than ever before, with geometry and meshing playing an integral part in the computer-aided engineering (CAE) simulation process. Generating accurate geometry and creating the most appropriate mesh remains the foundation of engineering simulation. …
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Thermodynamic Characterization of Hydrocarbons
Thermodynamic Characterization of Hydrocarbons
Thermodynamic Characterization of Hydrocarbons June 24, 2020 11 AM EDT / 3 pM GMT Venue: Online Thermodynamic modeling of mixtures of hydrocarbons is a challenging area in computational fluid dynamics. Single-component modeling remains fairly straightforward as it uses a unique saturation curve for examining fluids. However, the problem becomes more difficult when one deals with …
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Valor Process Preparation Webinar – Process Prep Overview
Valor Process Preparation Webinar – Process Prep Overview
Register For This Web Seminar Online - Jun 24, 2020 11:00 AM - 11:30 AM US/Pacific Register Overview Valor Process Preparation is the most complete solution for preparing manufacturing collateral on the market today. Learn about the latest released capability that has been delivered in the latest version as well as get a sneak preview …
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14 events,
WOST 2020
We would like to invite you to exchange knowledge about CAE-based product and process optimization. The conference offers a targeted range of information and further education in practice-oriented workshops as well as in cross-industry lectures. We are proud that our long-standing partnership with ANSYS culminated last year in the admission into the large ANSYS family. …
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WEBINAR: RF AMPLIFIER SIMULATION USING ADI MODELS WITHIN AWR DESIGN ENVIRONMENT
WEBINAR: RF AMPLIFIER SIMULATION USING ADI MODELS WITHIN AWR DESIGN ENVIRONMENT
Webinar Details RF Amplifier Simulation Using ADI Models Within AWR Design Environment Date: Thursday, June 25, 2020 Time: 10:00am PDT Questions about this event? Send email to: events@cadence.com This webinar will showcase the latest RF amplifier model library from Analog Devices, Inc. (ADI) that support the Cadence® AWR Design Environment® simulation platform, specifically AWR® Visual System Simulator™ (VSS) software. The capabilities of …
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Technology Day: Adopting Effective Power Analysis Strategies from System to Silicon
Technology Day: Adopting Effective Power Analysis Strategies from System to Silicon
Overview Power analysis is critical throughout the lifecycle of a program. Effective power analysis requires different strategies and tools depending on where you are in that lifecycle. In this webinar, we will cover the Cadence® solutions for power analysis starting with early system-level analysis, through RTL-level architecture/ microarchitecture, and finally to silicon signoff. Cadence tools …
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Locate and Solve ESD Design Challenges and Analyze Parasitic Networks Webinar
Locate and Solve ESD Design Challenges and Analyze Parasitic Networks Webinar
Overview: As geometries of integrated circuits get smaller and complex, electrostatic discharge (ESD) and Parasitic related design issues become prevalent. In this webinar we will show you a few methodologies to help reduce the design cycle by identifying ESD protection schemes in your netlist and assist in the verification of the point-to-point parasitic resistance between …
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FREE
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Trace Design for Crosstalk Reduction
Trace Design for Crosstalk Reduction
Trace Design for Crosstalk Reduction Description Presented by: Scott McMorrow Returning to basics, we’ll investigate the relationship of trace geometry to crosstalk in interconnect design, and draw some conclusions based on system constraints. Microstrip, stripline, and dual-stripline layer geometries will be examined, and simple rules are derived that can be used to quickly aid in …
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Combine Ansys Simulation Capabilities With Particleworks for Complicated Fluid Simulations
Combine Ansys Simulation Capabilities With Particleworks for Complicated Fluid Simulations
June 25, 2020 11 AM EDT / 3 PM GMT Venue: Online Particleworks is a mesh-free, liquid-flow simulation software based on the moving particle simulation (MPS) method, which is capable of complicated fluid simulations such as liquid dropping, mixing, lubrication, spraying, sloshing and splashing. It complements Fluent's high-resolution, high-accuracy free surface results. Coupling such complicated …
4 events,
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Complete RTL to GDSII Flow for “Analog on Top” Designs
Complete RTL to GDSII Flow for “Analog on Top” Designs
Register For This Web Seminar Online - Jun 29, 2020 9:00 AM - 10:00 AM US/Pacific Register Online - Jun 29, 2020 5:00 PM - 6:00 PM US/Pacific Register Overview Mentor will highlight our Tanner Digital Implementer (TDI) tool, powered by the Oasys Digital Synthesis and Nitro Place and Route engines, and its integration into …
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Complete RTL to GDSII Flow for “Analog on Top” Designs
Complete RTL to GDSII Flow for “Analog on Top” Designs
Register For This Web Seminar Online - Jun 29, 2020 9:00 AM - 10:00 AM US/Pacific Register Online - Jun 29, 2020 5:00 PM - 6:00 PM US/Pacific Register Overview Mentor will highlight our Tanner Digital Implementer (TDI) tool, powered by the Oasys Digital Synthesis and Nitro Place and Route engines, and its integration into …
Continue reading "Complete RTL to GDSII Flow for “Analog on Top” Designs"
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Rapid Electric Motor Design — Evaluation of a Permanent Magnet Motor Against the Performance Specification
Rapid Electric Motor Design — Evaluation of a Permanent Magnet Motor Against the Performance Specification
June 29, 2020 10:00 AM (EEDT) Venue: Online This webinar demonstrates how Ansys Motor-CAD can rapidly evaluate a candidate interior PM machine design using multiphysics analysis against the complete specification, including continuous torque/speed characteristics and drive cycle efficiency.
13 events,
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Introduction to Visualizer for the VHDL Users
Introduction to Visualizer for the VHDL Users
Register For This Web Seminar Online - Jun 30, 2020 8:00 AM - 9:00 AM US/Pacific Register Overview Complex testing and methodology with complex silicon require powerful but simple to use debug solutions. The Visualizer Debug Environment provides a common debug solution for simulation, emulation and other engines, including Verilog, VHDL, UVM, SystemC, C/C++, Assertions …
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Addressing nm Mixed-Signal Verification Challenges with Symphony – Powered by the AFS Platform
Addressing nm Mixed-Signal Verification Challenges with Symphony – Powered by the AFS Platform
Register For This Web Seminar Online - Jun 30, 2020 8:00 AM - 9:00 AM US/Pacific Register Online - Jun 30, 2020 3:00 PM - 4:00 PM US/Pacific Register Overview In this session we provide an in-depth overview of Mentor’s recently launched Symphony Mixed-Signal Platform. Symphony is the industry’s fastest and most configurable mixed-signal solution …
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Introduction to Visualizer for the VHDL Users
Introduction to Visualizer for the VHDL Users
Register For This Web Seminar Online - Jun 30, 2020 8:00 AM - 9:00 AM US/Pacific Register Overview Complex testing and methodology with complex silicon require powerful but simple to use debug solutions. The Visualizer Debug Environment provides a common debug solution for simulation, emulation and other engines, including Verilog, VHDL, UVM, SystemC, C/C++, Assertions …
Continue reading "Introduction to Visualizer for the VHDL Users"
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Addressing nm Mixed-Signal Verification Challenges with Symphony – Powered by the AFS Platform
Addressing nm Mixed-Signal Verification Challenges with Symphony – Powered by the AFS Platform
Register For This Web Seminar Online - Jun 30, 2020 8:00 AM - 9:00 AM US/Pacific Register Online - Jun 30, 2020 3:00 PM - 4:00 PM US/Pacific Register Overview In this session we provide an in-depth overview of Mentor’s recently launched Symphony Mixed-Signal Platform. Symphony is the industry’s fastest and most configurable mixed-signal solution …
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WEBINAR: Analog Verification and Characterization with Monte Carlo and High-Sigma Analysis
WEBINAR: Analog Verification and Characterization with Monte Carlo and High-Sigma Analysis
Semiconductor companies designing ICs for smart phones, automotive and industrial applications, CPUs, GPUs and memory components all employ teams of custom IC designers to create the highest performance chips that are as small as possible, and at the lowest costs. Designers must verify and characterize their IP’s sensitivity to random parametric variations in the manufacturing …
4 events,
Webinar Series: Digital Implementation and Signoff
Webinar Series Webinars are chosen during registration Reduce Iterations, Achieve Faster Design Closure Time with Innovus Implementation and Tempus ECO Option Wednesday, July 1, 2020 15:00 UKT / 16:00 CEST / 17:00 EEST/IDT / 10:00 AM EDT Speaker: Thierry Sarrazin The Cadence® Tempus™ Timing Signoff Solution is integrated with the Innovus™ Implementation System where it …
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Webinar: Improve Device Matching with Assisted Component P&R
Webinar: Improve Device Matching with Assisted Component P&R
Overview The increased analog content of today’s ICs needs more automation and reuse during the custom layout process. These circuits frequently use structures requiring precise matching of device characteristics. Module generators (ModGens) in the Cadence® Virtuoso® Layout Suite address these precise matching requirements in analog layout. They allow you to create highly matched arrays of devices directly …
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In-System Safety and Reliability for Automotive SoCs using Innovative Memory IP
In-System Safety and Reliability for Automotive SoCs using Innovative Memory IP
In the emerging era of large scale SoCs comprised from complex IP, typically designed for AI and automotive applications, designers must embrace an innovative approach to overcome numerous safety and reliability challenges. Therefore, the solution must be scalable, robust and Functional Safety (FuSa) aware, in addition to meeting fast-time to market aspect. This webinar presents …
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