WEBINAR: Chipmakers can leverage generative AI to speed up RTL design and verification

The subjects of Generative AI and Large Language Models (LLMs) permeate businesses and the public conversation.  It’s not without good reason!  While this emergent field of AI develops, it is now seen at a minimum as a valuable assistant, or, often, a dramatic accelerant to productivity, even to technical workflows.

As we’re now seeing with AI-assisted coding in software development, generative AI will play a similar role in IC logic design and verification with the same dramatic effect.  Increasing in criticality, centralized requirements will be the foundational source of truth for both human engineers and automated “AI assistants” responsible for writing RTL and verification requirements, executing tests, ultimately shrinking time to market.

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AI-assisted Software Dev: Requirements to Code

Applications of generative AI are disrupting traditional tech-centric fields, like pure software application development where we see movement from all-human to AI-assisted coding.  Tools like GitHub Copilot can act as your micro-level pair programmer. Even with minimal access to small portions of your codebase, it assists developers by proposing sections of code on demand.  Copilot is limited, in part, by its inability to understand the high-level requirements that drive the code.  AI needs the human-developer to interpret the human-readable requirements and thus, clocks out when the developer clocks out.

Software developers recognize this limitation and the community at large is working towards the audacious vision of full automation from centralized, human-readable requirements.  As large-scale commercial LLMs advance, alongside the open and more specialized language models, the fruits of these efforts are becoming increasingly tangible.  Nascent projects like GPT-Engineer, Aider, and GPT-Pilot are blazing the trail and moving us closer to this vision of automated 24×7 requirements to code software development.

AI-accelerated RTL Design and Verification

Clearly documented requirements as a single source of truth are key in automating development with generative AI.  We see logic design and verification activities ideally suited to AI-accelerated development, unlike pure software development discussed prior. Pure software applications have human-centric GUI’s which AI has yet to automate. To compound, software often suffers from poorly documented requirements which lead to bugs.

By contrast, the logic designed into semiconductor chips originates from rigorous, well-documented specifications – ripe to be accurately interpreted through LLMs. The requirements (or specs) are the bedrock of the entire IC logic design and verification endeavor. Whether the work is carried out by skilled engineers or sophisticated AI assistants, these detailed specifications serve as the single source of truth upon which every aspect of the design is built.

To fully harness the potential of AI assistants, organizations will be tasked to build out AI systems that have access to a unified hub for all product documentation and specifications. This is key now in human-centric workflows but will become mission critical as design and verification is accelerated by AI assisted processes. It’s imperative that these AI systems have access to a unified hub for all product information to ensure that AI tools are aligned with the overarching requirements, operating within the same framework of understanding as their human engineering counterparts.

Meet Sinfonia in our upcoming webinar

Planorama Design is laser focused on the problems of traditional software and IC design and development. We strongly believe that solid, rigorously documented requirements and user experience design are the catalysts to accelerate software and software-hardware (IoT) systems time to market.  To accelerate our internal processes and enhance our tools, Planorama Design built Sinfonia from the ground up with a focus on centralization of requirements.

On March 21, 2024 join us for our webinar, “From Specs to Verilog: AI-assisted logic design on a RISC-V implementation” where we will demonstrate Sinfonia.  In this webinar, we will show how Sinfonia, with knowledge of RISC-V specification documents can support user-directed enhancements to an existing RISC-V implementation. This approach exemplifies the potential of AI to accelerate logic design and verification, offering a glimpse into future engineering capabilities available to semiconductor and hardware companies.

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Learn more about Sinfonia

Connect with Matt Genovese of Planorama

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