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Events
Posted on by Daniel Payne

A 3D Field Solver for Parasitic Extraction Thermal ESD Analysis

A 3D Field Solver for Parasitic Extraction Thermal ESD Analysis
by Daniel Payne on 06-27-2013 at 2:38 pm
Categories: EDA, Events

The smaller the process node the more necessary it is that you extract accurate parasitics from interconnect and 3D structures in order to analyze timing, thermal effects and ESD compliance. Silicon Frontlinehas EDA tools in all three of these categories, so I met with Dermott Lynchat DAC to get an annual update.


Dermott Lynch, 3rd from left

Q: Can you give me a quick overview of your EDA tools?

Products – F3D (1st product), fast 3d parasitic extraction

– R3D, R3D Gate , analysis of power and ESD

– (New) Ethan – electro thermal analysis of Power and ESD Devices
focused on Power devices (not like full-chip analysis by Apache or Gradient). Power devices are much more complex to analyze. Movie of thermal is the type of analysis provided. Analysis could take hours of analysis to create one movie, multi seconds of movie would take days. Announced in May, being used by a handful of companies. High temperature gradients can cause cracking,mechanical issues cause by temp gradients.

Automotive – really need to know the reliability of their chips related to temperatures

Accuracy – silicon can be measured and verified versus simulation, within a few degrees.

Technologies – Bipolar, BCD, CMOS, DMOS, LDMOS, etc. Take the PDK info and create a tech file, customers can create their own tech file, not a big deal.

Ethan – where to place my thermal sensor on my chip?

ESRA (one year old) – full chip ESD analysis for HBM, CDM and MM events. Are my ESD devices reliable based on R and non-uniform flow. Where should my contacts be placed? Detailed ESD device analysis. (ESD Reliability Analysis)

– are my ESD devices being over designed? What can be scaled? Understand both R and C very detailed with the 3D field solver. Run on netlists with 22 billion transistors for ESD compliance, show me the hotspots.Run time: number of pins, power domains, overnight run time for the billions case.
– global report with violations, then detailed reports of violation.
– capacity of billions with ESRA is faster than Calibre PERC, because we are not taking any shortcuts.

P2P – Point 2 point resistance analysis, IR Drop, EM. Array-based design groups: Sensor arrays. How do I layout a complex power grid? Quick way to analyze this layout structure. Power grid analysis primarily. reports are graphical and textual in nature.

Q: How is business for you this year?

Growth – doubling our business in 2013, again. Hiring, device physics, AE, power device design, EM, thermal, developers, Silicon Valley or Belaruse.

Q: How are you funded?

Privately funded plus VC funding, angel funding.

Q: What is the size of your company?

Staff of 25 by eoy, if hiring goals met.

Q: What are the trends that you see at DAC this year?

At DAC the economy is coming back in growth mode again, cautious EDA buyers are more optimistic this year, must have tools are growing in demand.

Q: Are your tools in the TSMC reference flows?

Yes, TSMC reference AMS flow – F3D.

X-FAB – R3D is in their flow.

Tower Jazz, Dongbu, UMC – recommend our tools.

lang: en_US

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