Webinar: Using Veloce PCD to implement an Arm CSS with confidence

Software Defines Everything
For today’s SoC and system designs, hardware is designed and optimized for the software workload. Workloads can include firmware, multi-OS architectures, AI/ML and complex graphics. These combined produce large software models that put pressure on system-level verification.

What is the Arm Compute Subsystem (CSS)  
A compute subsystem is a pre-integrated, optimized hardware and software solution that simplifies the development of complex applications by providing a standardized framework for integrating processors with various peripherals and other system components.

The Arm CSS portfolio is highly configurable, optimized for performance, and includes a full system-ready SoC reference design. With it, companies can create any combination of IP and CSS to work with standard software. In addition to the CSS, customers need a qualified verification solution to tie everything together in one view so they can focus on creating unique IP.

Veloce PCIe Composite Device  
Today, we will use an example chiplet AI accelerator design to illustration the importance of Siemens Veloce verification technology called PCIe Composite Device (PCD). Veloce PCD is a combination of VLAB interface solutions (PCIe, NVMe, Arm Compliance Suite) in one product with a single Protocol Analyzer view of multiple interfaces.

We’ll cover the following:

• Connecting each interface to a Transactor or VLAB models
  • Connected interfaces mixed and matched between CXL, PCIe supporting complex P2P communication, i.e. Flit mode to non-flit mode
• Virtual Models mix and match on each interface for autonomous reactive host or device models
• Protocol Analyzer provides full multi-chiplet view for performance analysis
• How Arm Compliance Suite provides complete regression stimulus automatically
• Veloce CS capacity scaling to handle these large systems efficiently