Join the Discussion: Foundry ESD Checks & Standardized ESD Compact Models at US-IEW 2025

The ever-evolving landscape of semiconductor design demands robust ESD protection strategies that balance performance, reliability, and compliance. At the 2025 International Electrostatic Discharge Workshop (US-IEW), industry leaders will come together to tackle two of the most pressing topics in ESD: Foundry ESD Checks and IC Requirements and Standardized ESD Compact Models. We’re excited to announce that Stephen Fairbanks, CEO and CTO of Certus Semiconductor, will be a panelist in both of these must-attend discussions.

Panel 1: Foundry ESD Checks and IC Requirements

📅 April 2, 2025 | 2:45 PM – 5:45 PM
📍 US-IEW 2025

Moderated by Slavica Malobabic (Cirrus), this distinguished panel will explore the complexities of ESD sign-off processes when incorporating foundry rules. While foundries provide rule decks for latch-up, HBM, and CDM protections, challenges arise when these checks fail to consider specific pin types, voltage conditions, and parasitic effects. Attendees will gain insights into:

• Strategies for managing foundry ESD rule flags and risk assessments.
• The role of in-house vs. commercial ESD tools for sign-off.
• Enhanced static vs. dynamic ESD verification methods.
• The availability and limitations of foundry-supplied SOA (Safe Operating Area) data.

Stephen Fairbanks will join fellow panelists from Ansys, Cadence, Siemens, Tower, Skywater, and TSMC to share his expertise on navigating and enhancing the foundry ESD rule-checking process.

Panel 2: Standardized ESD Compact Models

📅 April 3, 2025 | 1:30 PM – 3:50 PM
📍 US-IEW 2025

With the increasing demand for first-time-right ESD design, standardized compact models play a crucial role in semiconductor innovation. This panel, moderated by Michi Stockinger (NXP), will focus on the latest advancements in ESD compact modeling, particularly the adoption of ASM-ESD diode and ESD FET snapback models.

Key discussion points include:

• How standardized models can improve ESD protection in advanced CMOS technologies.
• The tradeoff between high-speed I/O performance and ESD robustness.
• The role of TLP testing and modeling techniques in accurate SPICE simulations.
• The future of ESD modeling and its integration into foundry PDKs.

Stephen Fairbanks, alongside experts from UIIC, TSMC, and NXP, will offer insights into the evolving ESD compact model landscape and its impact on semiconductor reliability.

Why You Should Attend

These panels are designed for ESD engineers, foundry experts, EDA tool vendors, and IP providers who are looking to stay ahead in the ever-evolving world of ESD verification and modeling. Whether you’re actively working on ESD solutions or simply interested in learning more about the latest industry trends, these discussions will provide valuable technical insights and networking opportunities.

We invite you to join us at US-IEW 2025 to be part of these important conversations. Don’t miss the chance to hear from Stephen Fairbanks and other industry leaders as they share their expertise on the future of ESD protection in semiconductor design.

For more details on the workshop, visit esda.org/event/ or reach out to us at info@certus-semi.com.

REGISTER HERE