Acceleration of Complex RISC-V Processor Verification Using Test Generation Integrated with Hardware Emulation

The rapid evolution of RISC-V processors has introduced unprecedented verification challenges. Modern high-end RISC-V cores now incorporate complex features such as vector and hypervisor extensions, virtual memory systems, multi-level caches, advanced interrupt architectures, and multi-hart out-of-order execution. While these capabilities enable powerful and flexible processor designs, they also dramatically increase verification complexity. To ensure correctness and quality, verification methodologies must evolve to handle massive state spaces, long-running workloads, and extreme performance demands.

One of the most striking realities of contemporary RISC-V verification is the sheer scale of execution required. Verifying a typical high-end RISC-V core can demand on the order of 10¹⁵ cycles—far beyond the reach of traditional simulation alone. Effective verification therefore requires three essential components: stimulus derived from deep understanding of the RISC-V specification, complex and lengthy test programs that drive the design into meaningful microarchitectural states, and a fast execution platform capable of achieving verification closure within practical timelines.

The XiangShan RISC-V core exemplifies these challenges. Supporting RV64 with extensive extensions such as RVV 1.0, advanced memory management, large cache hierarchies with ECC, multi-level TLBs, and AIA-compliant interrupt handling, the design represents a realistic, high-complexity target. Verifying such a design requires stress-testing interactions across caches, memory ordering, interrupts, and multi-hart execution—scenarios that cannot be adequately covered by short, isolated tests.

To address these needs, Synopsys introduces STING, a bare-metal test generator purpose-built for RISC-V processor verification. STING employs a software-driven methodology that integrates multiple test generation approaches, including random stimulus, directed tests, workloads, and real-world scenarios. It generates both self-checking and pure stimulus tests that are portable across simulation, emulation, FPGA prototypes, and silicon. With comprehensive support for 32-bit and 64-bit RISC-V specifications, privilege modes, memory protection, virtualization, and multi-hart configurations, STING provides a scalable and reusable verification foundation. Its extensive library of over 100,000 test fragments enables rapid construction of complex test programs tailored to specific microarchitectural goals.

However, generating effective stimulus is only half the solution. Advanced RISC-V features such as cache coherency, memory ordering, atomicity, and synchronization demand long-running workloads to expose subtle corner cases. Scenarios involving true and false sharing, cache evictions, conflicting traffic, and fence ordering require sustained execution under varied conditions. For multi-processor platforms, repeating the same test sequence across different scheduling interleavings is essential to achieve thorough coverage. These demands make fast execution platforms indispensable.

Hardware-assisted verification (HAV) provides the necessary performance boost. By synthesizing the design under test and running it on emulation or prototyping platforms such as Synopsys ZeBu or HAPS, verification teams can execute tests at speeds orders of magnitude faster than simulation. In this approach, STING generates self-checking tests that embed reference model results directly into the executable. Tests are generated in parallel and streamed continuously into the hardware platform, ensuring that execution units remain fully utilized.

The streaming methodology is a key innovation in this solution. By avoiding repeated hardware re-initialization and redundant configuration cycles, and by enabling concurrent test generation and execution, streaming dramatically improves throughput. Results demonstrate performance improvements of up to 6000× per test when moving from simulation to emulation, making large-scale regression feasible for complex RISC-V designs.

Debugging failures discovered in high-speed regressions presents its own challenges. Because failures may depend on accumulated microarchitectural state across multiple tests, simple re-execution may not reproduce the issue. The recommended strategy involves replaying sequences of streaming-enabled tests to reconstruct the failing conditions. Hardware/software debug using tools such as Verdi enables synchronized analysis of CPU traces and waveforms, allowing engineers to step through execution while correlating software behavior with hardware signals.

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Bottom line: Accelerating complex RISC-V processor verification requires a tightly integrated strategy combining intelligent test generation, hardware-assisted execution, and advanced debug methodologies. By uniting STING with high-performance emulation platforms, verification teams can achieve comprehensive stimulus coverage, unprecedented execution speed, and effective debug—making verification closure achievable even for today’s most sophisticated RISC-V processors.

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