Webinar – How to Reclaim Margin in Advanced Nodes

This informative webinar discusses a significant issue that is cropping up for sub-5nm designs. As the graphic above shows, modeling uncertainty at advanced nodes results in excessive guard banding. These guard bands result in reduced performance and profit. A loss of 25 – 35% in PPA is discussed, along with the lost profit associated with paying for advanced node performance and not being able to take advantage of it.

You will learn a lot about the dimensions of this problem and how to fix it, resulting in improved performance, competitiveness and profit. A replay link is coming but first let’s examine how to reclaim margin in advanced nodes.

The Presenter

Dave Johnson is the webinar presenter. Dave works on strategic sales at ClockEdge. Prior to his decades long career in EDA, Dave was an ASIC engineer specializing in custom IC development. He has worked with many of the largest semiconductor companies around the world to optimize their design flow. He is someone who believes deeply that the choice of design methodology matters, significantly impacting the project’s success.

Dave is quite knowledgeable on the topic of design margins. He has an easy-to-follow presentation style. You will learn a lot during this short (22-minute) webinar.

The Webinar

Dave begins by describing the margin problem as a silent crisis in advanced node design. He discusses the widespread use of abstractions to drive design of ever-larger chips. He describes the “abstraction tax” that results from the difference between the estimates that drive design margins when compared with the actual performance needed. Dave gets into the details of what drives this “abstraction tax” and what penalties result. He then discusses a new and unique solution that enables design teams to reclaim the wasted margin at advanced nodes so the true value of advanced processes can be realized.

He describes the pessimism wall that exist sub 5-nm. He goes on to explain that at 3nm, the foundry promises and design teams expect a 15-18% performance improvement at constant power, or a 30-34% power reduction at constant frequency.

He goes on to explain that these gains are vanishing due to the pessimism wall. Now, the primary performance bottleneck is not silicon capability, but an abstraction-based methodology. Margins are now heavily inflated to compensate for methodology uncertainty. For example, clock sign-off guard bands routinely consume 25-35% of the available clock period. This results in over-designing the network by 2.5X. The figure at the right summarizes these points.

Dave then explores the details of the abstraction tax. He discusses the areas that contribute to the problem, including near-threshold voltage sensitivity, power supply-induced jitter, interconnect-dominated clock delay, aging, and local variability and Liberty Variation Format (LVF) residuals. You will learn a lot about the impact all these items have.

Dave then explores the ROI associated with recovering the lost margin due to these effects. Performance, clock tree area, dynamic power and binning yield are all discussed.

An effective solution to these problems offered by ClockEdge is then explored in some detail. Dave explains how the ClockEdge Veridian Engine can deliver full clock SPICE-level analysis overnight for over 100 million gate designs. He explains the significant impact a tool like this can have on advanced node design, allowing the abstraction tax to be removed. Design teams can now access the full capability offered by advanced nodes.

The webinar concludes with a very informative question and answer session.

To Learn More

If you struggle to get all the benefits offered by advanced process nodes due to excessive design margins, you need to watch this webinar. In a short 22 minutes, you will understand the problem much better and learn about a new and effective solution to unlock superior performance and increased profitability.

You can access the webinar replay here. And that’s how to reclaim margin in advanced nodes.

What is the 3nm Pessimism Wall and Why is it An Economic Crisis?

The Risk of Not Optimizing Clock Power

Taming Advanced Node Clock Network Challenges: Jitter