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EDA
Posted on by Dan Clein

Is there anything in VLSI layout other than “pushing polygons”?

Is there anything in VLSI layout other than “pushing polygons”?
by Dan Clein on 09-12-2017 at 12:00 pm
Categories: EDA

As I travel a lot in the last 15 years and visited customers as well as friends I was many times invited to talk to the Layout teams. The main purpose is always to encourage automation. So I developed a presentation related to market trend, technology trends, and latest tools advancements. In many cases I present updates from DAC (Design Automation Conference), to which I am a big fan participating for more than 20 years. From Memory to Analog and Digital Place & Route in all cases the first question was:

Is there anything else we can do other than just layout? What is my future? What can I do to grow faster? What did you do?

Everybody is afraid that there is nothing else but schematic to layout or Netlist to P&R and their life will be as monotone as a production line work. Nothing more wrong to think about.

In the last 3 years I decided to add an answer to this question and everywhere I talk to layout and design teams I reveal this in a last 20 minutes. So I decided this time to share this is with all of you so you will be able to act before I come to visit your company and present. Will write a series of articles describing the tools in which I was involved as a Layout Designer, from internal to external. Will use approximate timeframe, as some happen 30 years ago, and will provide some context of the condition that enabled such involvement. Will add names of people who actually did the work, or managed it as I was only the instigator, advisor, or tester in many cases.

There are a few condition that favorited my involvement in these developments:
[LIST=1]

  • The Layout team encounters always the challenge of being the last in the chip design flow – so everything that is late or missed ahead in the design flow, falls on the layout team to “save the day”. If and when the Management analyses the full flow it is obvious that the biggest issue is not layout creation but the ECO (Engineering Change Order) or changes to post layout simulations. So only when somebody looks at the full flow can understand that the sooner you bring layout (physical information) into circuit simulations the faster and more predictable gets the flow. From floorplan to placement, from routing to final layout clean from verification, layout is always “somehow” in the hot seat. So if you want change something work on the FLOW.
  • I was a lucky guy to start working in MSIL (Motorola Semiconductor Israel). Our CEO at that time Zvi Soha cared only about tapeout (and at that time this meant a real tape 19 inch diameter going out with the final chip GDSII). He wanted MSIL to be the best site within Motorola Semiconductor, so he enabled internal cooperation between teams and supported any new tools development that can support his plan, even so sometimes against the corporate “policies”. Not too many companies even today, have meetings between CAD, Circuit Design, Layout Design, etc., to enable flow automation as a whole not only as a section of it. PMC Sierra with Norbert Diesing Mixed Signal CAD had a “cooperation group” for support and roadmaps, but no resources to build new tools.
  • The hardware and software were all over the map. The front end design was divided in 2 sections: the system and functional simulations were done on IBM mainframe (cooled with water in a climate controlled room) and the circuit design was done on Daisy machines and software. The layout was done on Calma, a computer made by Data General (mainframe) with 4 terminals, each with 2 monitors, one text and one graphics. We did not have a mouse with 3 functions but a pen and a menu on the screen (taking very valuable visual rea). The pictures attached show a terminal of S-140 machine taken from the web.
  • The verification was done on the IBM using a software called MASKAP, for which Motorola had the source code. So you had to write a tape from Calma and load onto IBM to run verification then write the results on tape and upload into Calma. We had a parser for the DRC images (errors polygons) on Calma screen and a printed error file to identify what is actually the error. A very tedious work I may say…
  • I was a new immigrant to Israel and had problems with Hebrew. All the technology was in English so I focused on getting better at that, as this was a familiar language from my school days. The only way to move ahead was to add value to my knowledge, to be better at something that for others may not be of interest. Calma needed a workstation in the “cold room” the one with the server, so coming from Romania I was the most acclimatized to use it. We had shifts as we had 4 terminals and 8 people but if you used the cold room terminal you can stay longer without bothering others. So I started to read all CALMA manuals, in 3 months I knew enough to be “dangerous”.

    First step in starting my non-layout involvement was from an error. We taped out a chip verified and qualified “free of errors” but it came back with a short. As most of the work in 1984 was in multiples of microns polysilicon size 45 degree polygons where not needed. At that time the technology had only 1 (one) metal routing and we did route 45 degrees but not poly (which was used for GATE and for routing). However somebody used poly in 45 degree and the verification deck did not cover that. On the screen we could see the error between ad poly/metal 1 contact distance to a 45 degree poly as “below accepted distance” but in silicon was a real short. MSIL was only doing development using all verification decks provided by Austin, TX. After that date Zvi decided that we should have our own verification calibration done locally. So from the CAD department was assigned a very new software expert, Karina (later married Ben-Tvi) who needed a layout person to build all layout test cases for verification. Guess what, even so this was a simple task, below an interesting layout challenge, I volunteered thinking that this can widen my horizon.

    This was my first experience outside “layout” and working with Karina was a pleasure. We started daily meetings to figure out how to do this as no documentation was available, and we were doing it, kind of“under the table”. After about 3 months we had our own MSIL DRC deck. But with good food comes more appetite for automation. By end of 1985 we had additional checks not related to manufacturing but related to “good layout design practices”… Some of you may be aware that DRC and LVS actually have an underline ERC running, specifically these days with multiple voltages supplies. We developed our first SOFT CHECK by connecting one piece of diffusion at 2 difference voltages (text base) and found out a new verification that Motorola did not have. We proposed it to the headquarters and this is when they learnt that we have our own calibration in-house. As we had metal gates for input/output buffers (!) we added verification for that also, as the corporate delivered them “as is” and we were not allowed to modify them. After that working with CAD became a routine. Calma language was called GPL and we (all the layout team) wrote some small scripts to open the chip (it was taking one (1) hour to open top level, to add text, to move screens for routing, etc. But none of us was really trained for software and working with CAD proved to be a solid extension of capabilities.

    More about how a layout designer can have “spice” in their profession next time.

    Dan Clein
    CMOS IC Layout Concepts, Methodologies and Tools

    Also Read: Is there anything in VLSI layout other than pushing polygons? (2)

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