Its a bouncing baby IEEE standard!

Pass the cigars! On November 3rd, 2014, the IEEE-SA Standards Board finally approved IEEE P1687 as a new standard. From now on, you can drop the “P” and just call it 1687, or to its friends, IJTAG. Now would be a good time to sign up for an IJTAG technical workshop.

The new IEEE 1687 Internal JTAG (IJTAG) standard is changing the way the industry validates, tests and debugs chips and circuit boards. It builds upon the popular IEEE 1149.1 JTAG board-level test access standard with a set of uniform methods to describe chip internal IP blocks, which are referred to within the standard as “instruments.” IJTAG-based methods are more cost-effective, more accurate, faster and less time-consuming for you than legacy probe-based technologies like an oscilloscope. IJTAG’s software-driven tests and validation routines are initiated from instruments embedded inside chips.

IJTAG is exciting because it addresses the complex issue of testing a heterogenous set of embedded IP. The traditional situation is that the interface for communicating control sequences, and the sequences themselves, are defined by IP developers in a wide variety of different styles with little commonality. Therefore, it falls to the designers to create unique logic to integrate each embedded instrument into an overall design. For SoCs that often have literally hundreds of instruments from a variety of sources with disparate interface styles, this is a major undertaking that typically requires large engineering resource and time. The new IJTAG standard is designed to solve this problem by providing a method for plug-and-play IP integration enabling communication to all the instruments from a single access point (generally an IEEE 1149.1 TAP).

It standardizes a language for describing the IP interface and how IPs are connected to each other. It introduces a new language that defines how patterns that operate or test the IP are to be described. And, there are already automation tools available to simplify the process of connecting any number of IJTAG compliant IP blocks into an integrated network for uniform access and control.

IJTAG has some traction already because it is useful to both IP providers and to chip designers. For IP providers, it makes their products easier to integrate and therefore more attractive to a wider customer base. It also gives them better testing and debugging capabilities as well as an overall more robust product. For chip integrators, the standard also expands the availability of IP sources by eliminating integration uncertainties and incompatibilities as well as provides increased scalability for rapidly growing design sizes.

There’s already been a lot of work with IJTAG. This 2012 whitepaper from Mentor Graphics and NXP Semiconductors details how they implemented P1687 on mixed-signal IPs in a 65 nm automotive design. The results show significant advantages of P1687 over the IEEE 1149.1 (JTAG) test methodology, both in automating the test pattern development and in reducing test setup data volume by more than 50%. The latest news is from Asset Intertech and talks about how interoperability between vendors tools allows IJTAG to be used easily at both chip and board level.

IJTAG is exciting because it addresses the complex issue of testing a heterogenous set of embedded IP. It standardizes a language for describing the IP interface and how IPs are connected to each other. It introduces a new language that defines how patterns that operate or test the IP are to be described. There are tools available to simplify the process of connecting any number of IJTAG compliant IP blocks into an integrated network for uniform access and control. This lets you send commands to the blocks from a single top-level access point (a TAP).

Asset and Mentor have also teamed up to present a series of technical workshops on IEEE 1687 across the world. You can register here.

Has anyone already started using IJTAG? Do you plan to look into it now that the standard is ratified?