Managing Stress in 3D

A new publication on mechanical stress in integrated circuits, co-edited by Valeriy Sukharev, Principal Engineer for Calibre R&D at Mentor Graphics, has just been released by AIP Publishing. “Stress-Induced Phenomena and Reliability in 3D Microelectronics” includes 14 key papers from four international workshops held in the U.S., Germany and Japan and is available at http://bit.ly/1w1svjo. The publication isn’t free, you’ll need to buy ($28) or rent ($4) it.

Development of 3D IC integration provides a potential solution to overcome the wiring limit imposing on interconnect density, performance and power consumption of integrated circuits. Management of mechanical stress is one of the key enablers for the successful implementation of 3D-integrated circuits using through silicon vias (TSVs). The potential stress-related impact of the 3D integration process on product reliability must be understood and shared, and designers need a solution for managing stress.

The co-editors selected papers to focus on Design-for-Reliability (DFR) and together they describe a stress management simulation flow that would enable designers to model stress implications on their designs quantitatively. The papers also discuss multi-scale modelling and simulation, multi-scale materials parameters and multi-scale analysis.

This is the second work in a series on stress management. The first publication, called “Stress Management for 3D ICS Using Through Silicon Vias” is available at http://amzn.to/1o60QE4.