IC place and route is a big challenge so we see many EDA companies creating tools. On Tuesday at DAC I met with Dave Noble of Pulsic to get an update.
Notes
Dave Noble, VP Operations (EDA since 2003), Sperry Univac since 1974
– had been an EDA distributor for Pulsic as well
More leads qualified on Monday than all days of last year at DAC.
What’s new this year?
History
12 years old, technology from Zuken, a shape-based router with Japanese customers. Toshiba and Renesas steered the company to do analog routing. A tool to complement the skills of an IC layout designer, not replacing their job.
Take a 6 week manual route into one day, you still have to control the process. Automation or interactive routing, it’s your choice.
SHort learning curve by designs, easy to setup constraints, not a week long learning. Own GUI, not an integration into Cadence GUI. ROuting can be exported to OA.
Unity CUstom Digital Router – been around for 12 years now. Has STA built in to the tool flow, so you don’t have to exit the router to understanding timing impact.
Unity Analog Router – new this year. Not as automated as CiraNova, more intuitive to your existing analog flow. Constraints are annotated in the schematic. We distinquish between custom and analog IC layout. Analog centric routing. Online DRC by reading a Cadence deck.
– Could read a Calibre deck, but not there yet. TSMC has about 10 pages of rules for analog routing. Goal is DRC correct by design, also you can check and fix in a semi-automated fashion.
– Pyxis was a litho-aware router.
– Virtuoso : Custom router with some analog features.
– CiraNOva: Press the route button and hope for the best, but didn’t get what I wanted.
Unity Bus Planner – separate piece available.
CUstomers: Samsung, Micron, (DRAM, Flash, PCM). AMS companies in Japan and US, FPGA. Memory companies like the sophisticated shape-based approach for routing the IO. Network switching companies starting to use Pulsic routers.
Shape-based isn’t constrained to a grid, so results are more efficient with fewer jogs and vias. Not aimed at being an ASIC router company.
Reference flows at Foundry – most of our clients are IDMs so we aren’t qualified at TSMC and other foundries. Do have customers using 28nm at TSMC.
Development in the UK (Bristol, New Castle), Japan.
Privately held and funded. Growth plans – add analog routing. 2011 about 30% growth and 2012 about 25% growth. Hiring now.
Time based licenses, typically 3 years, including support and training.
Why you versus competitors? Manual routing is the primary competitor.
Evaluations: Used to be 9 months, now about 6 months. Set a criteria of success.
Any consulting services? Yes, we do some of that for our customers in terms of creating and optimizing a flow, working with their data.
3rd party: Cadence Connections, Mentor OPen Door, Synopsys inSync, SpringSoft.
12 months from now – continued revenue growth, more people (32 now), new products next year from internal development. Enough cash to last 3 years, so have conservative growth plans.
Japan – distributor is Jedat.
Release cycles – green build every 3 months, SCRUM methodology. Customers can track the progress of every bug filed, complete transparency.
Summary
Pulsic offers P&R tools for both digital and analog IC designers. They compete in a crowded market with: Cadence, Synposys (Magma), Mentor and A Toptech.
Next Generation of Systems Design at Siemens