eSilicon, in conjunction with King Research, is conducting an unusual survey. A lot of vendor-driven surveys focus on specific pain points that are addressed by that particular vendor’s product/service. The idea is typically to either promote visibility for the product/service or establish its undeniable need in the market.… Read More
Big Data, the Cloud and the Internet of (Silicon) Things
Next week, eSilicon are kicking off a very widespread survey to measure some important semiconductor design and manufacturing challenges. Their goal is to measure customer sentiment regarding how Big Data, the Cloud and the Internet can impact these challenges. But here’s a secret, the survey is already live and you can… Read More
What Comes After FinFET?
So what comes after FinFETs? At 14/16nm (or 22nm if you are Intel) we had FinFET transistors, where the channel was no longer planar but stuck out of the wafer vertically, and the gate wrapped around it on 3 sides. The key thing that made FinFET transistors attractive was that the channel was thin so that the gate controlled it well. … Read More
Semiconductor Revenue Trends
Image Source: Wikipedia
Nescire autem quid ante quam natus sis acciderit, id est semper esse puerum. (Not to know what happened before you were born is to remain forever a child.)–Cicero
2014 is destined to be a pivotal year for Silicon Valley and High Tech in general. End user markets have been stagnating or declining over the last… Read More
eSilicon and the Ten Minute Quote
One of the challenges in bringing a design into production is getting a quote that includes all the various stages of the process. The quote cycle typically takes a couple of weeks. It is also pretty wasteful. A typical design might be quoted by 3 manufacturers and so 2 out of 3 quotes are wasted expense because the design is lost to a … Read More
EUV Pellicles
Shakespeare reckoned that a man went through seven stages in his life.All the world’s a stage, And all the men and women merely players. They have their exits and their entrances, And one man in his time plays many parts, His acts being seven ages.
Well, an EUV mask seems to only go through three main stages:
[LIST=1]
Getting a Tapeout Quote in 10 Minutes!
On Thursday, July 31[SUP]st[/SUP] at 8 AM Pacific Daylight Time I’ll be moderating a webinar that will demo eSilicon’s new GDSII quoting portal. You can find more details about the webinar here, and you can register here.
I’ve worked with a lot of companies that do advanced custom IC designs. Getting a quote that covers all the NRE… Read More
Moderate growth and minor correction in semiconductors
At SEMICON West two weeks ago, Bob Johnson of Gartner presented the outlook for the semiconductor market, semiconductor capital spending, and wafer fab equipment spending. Thanks to Daniel Nenni for providing the link to the SEMI/Gartner Market Symposium presentations at https://sites.google.com/a/semi.org/market-symposium/home/speaker-presentations… Read More
Setting the Record Straight on FD-SOI Costs
I recently published an article on Semiwiki “Is SOI Really Less Expensive”. That article was the result of months of careful research and analysis. I looked at planar FDSOI versus bulk planar, bulk FinFETs and FinFETs on SOI at three different nodes. I took a consistent set of assumptions with respect to the fab used to run the processes,… Read More
SEMICON Update: 450mm, EUV, FinFET, and More
I spent all of last week at SEMICON West meeting with customers, potential customers, partners and various industry analysts and experts. I was involved in many interesting discussions over the course of the week and I thought I would share some of the more interesting observations:
Alternate Fin Materials Pushed Out
I have for… Read More
Facing the Quantum Nature of EUV Lithography