In the rapidly evolving landscape of artificial intelligence (AI) and data-intensive applications, the demand for high-performance interconnect technologies has never been more critical. Even the 100G Interconnect is already not fast enough for infrastructure applications. AI applications, with their massive datasets… Read More
Semiconductor Intellectual Property
Ceva Launches New Brand Identity Reflecting its Focus on Smart Edge IP Innovation
Company sharpens its strategy of delivering silicon and software IP that makes it possible for low power Edge AI devices to connect, sense and infer data, reliably and efficiently, across multiple high-growth end markets
Ceva Inc. is an interesting company. Founded in November 2002, through the combination of the DSP IP licensing… Read More
RISC-V and Chiplets: A Panel Discussion
At the recent RISC-V Summit, the very last session was a panel about chiplets called Chiplets in the RISC-V Ecosystem. It was moderated by Calista Redmond, the CEO of RISC-V International. The panelists were:
- Laurent Moll, COO of Arteris
- Aniket Saha, VP of Product Management of Tenstorrent
- Dale Greenley, VP of Engineering of Ventana
When Will Structured Assembly Cross the Chasm?
First, a quick definition. By “structured assembly,” I mean the collection of tools to support IP packaging with standardized interfaces, SoC integration based on those IPs together with bus fabric and other connectivity hookups, register definition and management in support of hardware/software interface definition, … Read More
Automated Constraints Promotion Methodology for IP to Complex SoC Designs
In the world of semiconductor design, constraints are essentially specifications and requirements that guide the implementation of a specific hardware or software component within a larger system. They dictate timing, area, power, performance, and of course functionality of a design, playing a crucial role in ensuring that… Read More
UCIe InterOp Testchip Unleashes Growth of Open Chiplet Ecosystem
Intel recently made headlines when CEO Pat Gelsinger unveiled the world’s first UCIe interoperability test chip demo at Innovation 2023. The test chip built using advanced packaging technology is codenamed Pike Creek and is used to demonstrate interoperability across chiplets designed by Intel and Synopsys. More details … Read More
Podcast EP197: A Tour of the RISC-V Movement and SiFive’s Contributions with Jack Kang
Dan is joined by Jack Kang of SiFive. As a member of the founding team at SiFive, Jack oversees the Business Development, Customer Experience, and Corporate Marketing groups. He is responsible for strategic business initiatives and partnerships, technical pre-sales activities and post-sales support, and corporate messaging… Read More
CEO Interview: Suresh Sugumar of Mastiska AI
Suresh is a technology executive with deep technical expertise in semiconductors, artificial intelligence, cybersecurity, internet-of-things, hardware, software, etc. He spent 20 years in the industry, most recently serving as an Executive Director for open-source zero-trust chip development at Technology Innovation… Read More
5G Aim at LEO Satellites Will Stimulate Growth and Competition
Low earth orbit (LEO) satellites as an intermediary for communication became hot when Elon Musk announced Starlink (yeah, other options were available, but Elon Musk). This capability extends internet availability to remote areas and notably (for a while) to Ukraine in support of the war with Russia. Satellites can in principle… Read More
RISC-V Summit Buzz – Semidynamics Founder and CEO Roger Espasa Introduces Extreme Customization
Founded in 2016 and based in Barcelona, Spain, Semidynamics™ is the only provider of fully customizable RISC-V processor IP. The company delivers high bandwidth, high performance cores with vector units and tensor units targeted at machine learning and AI applications. There were some recent announcements from Semidynamics… Read More
Selling the Forges of the Future: U.S. Report Exposes China’s Reliance on Western Chip Tools