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CTO Interview with Ed Plowman of Imagination Technologies

CTO Interview with Ed Plowman of Imagination Technologies
by Daniel Nenni on 11-03-2026 at 12:00 pm

Turning TOPS into useful work

Ed Plowman is Chief Technology Officer at Imagination Technologies, where he leads technology strategy, advanced architecture research and long-term innovation initiatives. He focuses on the convergence of graphics, compute and artificial intelligence, helping shape the next generation of efficient and adaptable computing… Read More


IP update from Alphacore at DAC 2026

IP update from Alphacore at DAC 2026
by Daniel Payne on 11-03-2026 at 10:00 am

alphacore at dac 2026

Rusafa Shahreen, Director of Technical Marketing at Alphacore met with me at DAC 2026 to provide an update on what’s new in their IP for AMS, RF, imaging and rad-hard designs. Her background includes MSEE and MBA degrees, plus seven years at Alphacore in Arizona. The founders of the company have a rad-hard background and their early… Read More


Ceva’s next NeuPro generation opens new possibilities across AI

Ceva’s next NeuPro generation opens new possibilities across AI
by Daniel Nenni on 11-03-2026 at 8:00 am

CEVA NEUPRO NPU portfolio

Ceva is broadening the possibilities for AI silicon with a new generation of its NeuPro neural processing unit portfolio, bringing a common architecture and unified software environment to applications spanning sensors, intelligent devices and cloud infrastructure.

Announced on October 28, the portfolio reflects an opportunity:… Read More


Interview with Sweta Gupta, VP of Engineering of Analog Bits

Interview with Sweta Gupta, VP of Engineering of Analog Bits
by Daniel Nenni on 11-02-2026 at 12:00 pm

Sweta Gupta in analog innovation

Sweta Gupta is the Vice President of Engineering at Analog Bits, where she leads development and execution of mixed-signal IP’s, managing circuit and layout teams.

Ms. Gupta has been a part of the Analog Bits team since 2004 and she has successfully managed and delivered high quality IP’s including low jitter PLL’s, low power crystal… Read More


WEBINAR: Porting, Analysing & Optimising AI Models onto Edge GPUs

WEBINAR: Porting, Analysing & Optimising AI Models onto Edge GPUs
by Daniel Nenni on 11-02-2026 at 10:00 am

Edge GPU AI webinar banner

Modern AI models are opening up new possibilities at the edge. Turning those possibilities into responsive, efficient applications, however, requires more than choosing hardware with an impressive TOPS figure. Developers need to understand how models behave on their target devices, where performance is lost, and which optimisations… Read More


Ceva’s Next-Generation NeuPro Brings a Unified AI Platform from Sensors to Infrastructure

Ceva’s Next-Generation NeuPro Brings a Unified AI Platform from Sensors to Infrastructure
by Daniel Nenni on 10-28-2026 at 4:00 am

NeuPro Sensors to AI infrastructure

Ceva is expanding the reach of its neural processing technology with a next-generation NeuPro portfolio designed to serve everything from always-on sensors to AI infrastructure. The announcement introduces four NPU families sharing a common architecture and unified software stack, giving semiconductor developers a consistent… Read More


S2C Targets Faster RISC-V Bring-Up With Prototyping and AI

S2C Targets Faster RISC-V Bring-Up With Prototyping and AI
by Daniel Nenni on 10-27-2026 at 6:00 am

S2C advances RISC V FPGA development

S2C showcased FPGA prototyping and AI-assisted debugging at the sixth RISC-V Summit China, outlining how developers can validate complex processor designs and begin software development before first silicon. Its demonstrations connected three stages of that effort: running substantial RISC-V systems on FPGA hardware,… Read More


Inside the Silicon: Analog Bits N2P2 Test Chip

Inside the Silicon: Analog Bits N2P2 Test Chip
by Daniel Nenni on 10-23-2026 at 9:00 am

Crimson Chip Precision

The future of intelligent computing depends on silicon that delivers more performance within tighter power and thermal limits. Combining TSMC’s advanced process technology with Analog Bits’ analog and mixed-signal expertise, we help designers address those demands through local power regulation, supply monitoring, precision… Read More


CEO Interview with Lisa Spelman of Cornelis

CEO Interview with Lisa Spelman of Cornelis
by Daniel Nenni on 10-23-2026 at 6:00 am

Lisa Spelman The network as compute

Lisa Spelman is CEO of Cornelis, where she leads the company’s efforts to advance high-performance networking for AI and HPC infrastructure. She brings more than 20 years of experience across AI, cloud, enterprise infrastructure, data center operations, product strategy, and go-to-market leadership.

Before joining Cornelis,… Read More


Arteris FlexGen Opens Up Multi-Die Traffic Management for Non-Coherent Networks

Arteris FlexGen Opens Up Multi-Die Traffic Management for Non-Coherent Networks
by Bernard Murphy on 10-21-2026 at 6:00 am

MultiDie FlexGen

Last year I wrote about Arteris’ introduction of multi-die support for coherent NoCs. This is a very big deal because hyperscalers and OEMs are now building large systems that depend on multi-chiplet architectures and require efficient traffic management between chiplets, in one case as many as 12 compute, fabric/cache and … Read More