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Arteris Highlights a Path to Scalable Multi-Die Systems at the Chiplet Summit

Arteris Highlights a Path to Scalable Multi-Die Systems at the Chiplet Summit
by Mike Gianfagna on 03-23-2026 at 6:00 am

Arteris Highlights a Path to Scalable Multi Die Systems at the Chiplet Summit

At the recent Chiplet Summit, presentations, discussions and general participation could be broken down into a few broad categories. There were presentations of actual chiplet designs, either as building blocks or end products. There were presentations regarding design tools and methodologies to support and accelerate … Read More


Podcast EP336: How Quadric is Enabling Dramatic Improvements in Edge AI with Veer Kheterpal

Podcast EP336: How Quadric is Enabling Dramatic Improvements in Edge AI with Veer Kheterpal
by Daniel Nenni on 03-20-2026 at 10:00 am

Daniel is joined by Dr. Veer Kheterpal. Veer has founded three technology companies and possesses full-stack expertise spanning software to silicon across edge and datacenter applications. Currently, he is the CEO & co-founder of Quadric, a semiconductor IP licensing company that delivers the blueprints for efficient,… Read More


WEBINAR: HBM4E Advances Bandwidth Performance for AI Training

WEBINAR: HBM4E Advances Bandwidth Performance for AI Training
by Don Dingee on 03-19-2026 at 10:00 am

HBM advantage in AI training

The rapid proliferation of LLMs and other AI applications, and of high-end GPU platforms that run them, is putting intense pressure on the performance requirements for memory technologies. Designers need to be keenly aware of how to make the most of their memory and controller choices, which can be moving targets given the rapid… Read More


The First Real RISC-V AI Laptop

The First Real RISC-V AI Laptop
by Jonah McLeod on 03-17-2026 at 6:00 am

DC ROMA

At a workshop in Boston on February 27, something subtle but important happened. Developers sat down in front of a RISC-V laptop, installed Fedora, and ran a local large language model. No simulation. No dev board tethered to a monitor. A laptop.

For more than a decade, RISC-V advocates have promised that the open instruction set… Read More


Podcast EP335: The Far Reaching Impact of UCIe with Dr. Debendra Das Sharma

Podcast EP335: The Far Reaching Impact of UCIe with Dr. Debendra Das Sharma
by Daniel Nenni on 03-13-2026 at 10:00 am

Daniel is joined by Dr. Debendra Das Sharma, a Senior Fellow and Chief I/O architect in the Data Platforms and Artificial Intelligence Group at Intel. He is a member of the National Academy of Engineering (NAE), Fellow of IEEE, and Fellow of International Academy of AI Sciences. He is a leading expert on I/O subsystem and interface… Read More


The Next Hurdle AI Systems Must Clear

The Next Hurdle AI Systems Must Clear
by Bernard Murphy on 03-11-2026 at 6:00 am

datacenter surrounded by power plants

AI isn’t having an easy ride. The media and Wall Street swing wildly between extremes on any hint of a shift in AI sentiment. Dickens saw this coming: “It was the best of times, it was the worst of times, it was the age of wisdom, it was the age of foolishness, it was the epoch of belief, it was the epoch of incredulity, it was the season of Read More


The Evolution of RISC-V and the Role of Andes Technology in Building a Global Ecosystem

The Evolution of RISC-V and the Role of Andes Technology in Building a Global Ecosystem
by Daniel Nenni on 03-09-2026 at 10:00 am

RISC V Now Andes Conference

During my frequent trips to Taiwan as a foundry relationship professional I remember meeting Frankwell Lin, CEO of Andes, in Taiwan 15+ years ago. As I walked to TSMC HQ from the Hotel Royal (my second home for many years) Andes was about mid point and Frankwell’s door was always open. Sometimes just tea, sometimes technology,… Read More


Keynote: On-Package Chiplet Innovations with UCIe

Keynote: On-Package Chiplet Innovations with UCIe
by Daniel Nenni on 03-08-2026 at 4:00 pm

Chiplet Summit Keynote UCIe 2026

In the rapidly evolving landscape of semiconductor technology, the Universal Chiplet Interconnect Express (UCIe) emerges as a groundbreaking open standard designed to revolutionize on-package chiplet integrations. Presented by Dr. Debendra Das Sharma, Chair of the UCIe Consortium and Intel Senior Fellow, at the ChipletRead More


From Satellites to 5G: Ceva’s PentaG-NTN™ Lowers Barriers for Terminal Innovators

From Satellites to 5G: Ceva’s PentaG-NTN™ Lowers Barriers for Terminal Innovators
by Daniel Nenni on 03-05-2026 at 8:00 am

unnamed (3)

Ceva, Inc., a leading provider of silicon and software IP for the Smart Edge, has unveiled PentaG-NTN™, its groundbreaking 5G Advanced modem IP subsystem tailored for satellite user terminals in Low Earth Orbit (LEO) and Medium Earth Orbit (MEO) constellations. Announced at Mobile World Congress 2026 in Barcelona on March 3,… Read More


RVA23 Ends Speculation’s Monopoly in RISC-V CPUs

RVA23 Ends Speculation’s Monopoly in RISC-V CPUs
by Jonah McLeod on 03-04-2026 at 8:00 am

RVA23 Image

RVA23 marks a turning point in how mainstream CPUs are expected to scale performance. By making the RISC-V Vector Extension (RVV) mandatory, it elevates structured, explicit parallelism to the same architectural status as scalar execution. Vectors are no longer optional accelerators bolted onto speculation-heavy cores.… Read More