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Intel: Pushing EMIB Forward: Design Methodology Insights with Synopsys Tools

Intel: Pushing EMIB Forward: Design Methodology Insights with Synopsys Tools
by Daniel Nenni on 06-04-2026 at 6:00 am

synopsys intel linkedin update 1200x1200 v3

As advanced packaging becomes a critical enabler for next-generation semiconductor products, Intel continues to drive innovation through its Embedded Multi-die Interconnect Bridge (EMIB) technology. EMIB has emerged as a foundational packaging solution for heterogeneous integration, allowing multiple chiplets and… Read More


Why Europe Needs Its Own AI Supercomputing Platform

Why Europe Needs Its Own AI Supercomputing Platform
by Daniel Nenni on 06-02-2026 at 10:00 am

image (10)

The strategic cooperation between Semidynamics and SiPearl to develop a European sovereign rack-scale AI compute platform is important for reasons that extend far beyond technology. It represents a major step toward Europe gaining greater control over its artificial intelligence infrastructure, reducing dependence on… Read More


Breaking the Clock Lane Barrier: MIPI C-PHY/D-PHY Combo IP on TSMC N2P

Breaking the Clock Lane Barrier: MIPI C-PHY/D-PHY Combo IP on TSMC N2P
by Daniel Nenni on 06-01-2026 at 6:00 am

Mixel MIPI 2026

The transition to advanced process nodes is reshaping high-speed interface IP requirements for mobile, automotive, AR/VR, and AI edge devices. As SoC designers migrate to cutting-edge foundry technologies, the demand for highly optimized MIPI PHY solutions continues to grow. A key development in this space is the availability… Read More


CFrame60: Rewriting the Rules of Frame Compression

CFrame60: Rewriting the Rules of Frame Compression
by Daniel Nenni on 05-28-2026 at 8:00 am

CFrame60 Rewriting the Rules of Frame Compression

Chips&Media CFrame60 is a next-generation frame compression hardware IP designed to address the growing bandwidth and memory challenges in modern SoCs targeting imaging, video, AI, and display applications. Unlike conventional compression architectures that prioritize either bandwidth reduction or image quality,… Read More


SRAM compilers targeting automotive SoCs on advanced nodes

SRAM compilers targeting automotive SoCs on advanced nodes
by Don Dingee on 05-27-2026 at 6:00 am

Automotive versus consumer grade reliability

Processor IP garners the most attention in SoC design, but it’s not the only IP category begging for smart choices. Every processor core needs to be fed with data; however, frequent off-chip DRAM access incurs a large clock-cycle penalty each time. Architects now want SRAM blocks distributed throughout an SoC, putting data close… Read More


CEVA Accelerates Wireless Edge Innovation with Bluetooth HDT and Integrated RF Design Win

CEVA Accelerates Wireless Edge Innovation with Bluetooth HDT and Integrated RF Design Win
by Daniel Nenni on 05-26-2026 at 10:00 am

CEVA Accelerates Wireless Edge Innovation with Bluetooth HDT and Integrated RF Design Win

CEVA, the leading licensor of wireless connectivity and smart sensing technologies, is advancing its full-stack wireless strategy with the introduction of next-generation Bluetooth High Data Throughput (HDT) capabilities and a major integrated RF subsystem design win. The announcement underscores CEVA’s growing role… Read More


What Winemakers and Chip Designers Have in Common

What Winemakers and Chip Designers Have in Common
by Daniel Nenni on 05-22-2026 at 6:00 am

What Winemakers and Chip Designers Have in Common

Consider this a standout presentation at the Silicon Catalyst Spring Portfolio Update Meeting held yesterday at the Computer History Museum. Mahesh Tirupattur, CEO of Analog Bits, is a modern-day, multidimensional semiconductor hero and one of my trusted few. Analog Bits is a premier member of the semiconductor ecosystem,… Read More


Semidynamics Secures a Strategic Investment to Advance Memory-Centric AI Inference Chips

Semidynamics Secures a Strategic Investment to Advance Memory-Centric AI Inference Chips
by Daniel Nenni on 05-20-2026 at 8:00 am

Semidynamics Secures a Strategic Investment

In the rapidly evolving world of artificial intelligence hardware, memory bandwidth and data movement have become just as important as raw compute power. Addressing this challenge head-on, Semidynamics has announced a strategic investment aimed at accelerating the development of its next-generation memory-centric AI … Read More


The “New Shift-Left”: Why FPGA Prototyping is the Ultimate RISC-V IP Sandbox

The “New Shift-Left”: Why FPGA Prototyping is the Ultimate RISC-V IP Sandbox
by Daniel Nenni on 05-14-2026 at 10:00 am

Cover pic

In the EDA world, “Shift-Left” has traditionally been a mantra for early software development—booting the OS before the silicon even leaves the fab. But as the RISC-V revolution accelerates, the goalposts have moved. We are seeing the emergence of a “New Shift-Left”, one that focuses on critical architectural… Read More


SiFive’s P570 Gen 3 Pushes RISC-V Further Into the AI Era

SiFive’s P570 Gen 3 Pushes RISC-V Further Into the AI Era
by Kalar Rajendiran on 05-14-2026 at 6:00 am

P400 P500 Performance Family

With the launch of its new P570 Gen 3 processor family, SiFive is making a broader statement about the future of edge computing and the growing role of RISC-V in mainstream application processors. Rather than simply unveiling another CPU core, the company is positioning the P570 as a balanced-performance processor built specifically… Read More