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Google’s Road Trip to RISC-V at Warehouse Scale: Insights from Google’s Martin Dixon

Google’s Road Trip to RISC-V at Warehouse Scale: Insights from Google’s Martin Dixon
by Daniel Nenni on 12-21-2025 at 3:00 pm

Google RISC V in Datacenter 2025

In a engaging presentation at a recent RISC-V summit, Martin Dixon, Google’s Director of Data Center Performance Engineering, took the audience on a metaphorical “road trip” to explore the company’s vision for integrating RISC-V into its massive warehouse-scale computing infrastructure. Drawing… Read More


Bridging Embedded and Cloud Worlds: AWS Solutions for RISC-V Development

Bridging Embedded and Cloud Worlds: AWS Solutions for RISC-V Development
by Daniel Nenni on 12-21-2025 at 1:00 pm

AWS RISC V Summit 2025 SemiWiki

In a compelling keynote at the RISC-V Summit North America 2025, Jeremy Dahan from AWS explored the challenges of embedded systems development and how cloud technologies can bridge the gap between local hardware tinkering and scalable, shareable environments. Drawing from his experience as an engineer, Dahan highlighted … Read More


Navigating SoC Tradeoffs from IP to Ecosystem

Navigating SoC Tradeoffs from IP to Ecosystem
by Daniel Nenni on 12-17-2025 at 8:00 am

Building an SoC is Hard 2025

Building a complex SoC is a risky endeavor that demands careful planning, strategic decisions, and collaboration across hardware and software domains. As highlighted in Darren Jones’ RISC-V Summit presentation from Andes Technology, titled “From Blueprint to Reality: Navigating SoC Tradeoffs, IP, and Ecosystem,”… Read More


S2C, MachineWare, and Andes Introduce RISC-V Co-Emulation Solution to Accelerate Chip Development

S2C, MachineWare, and Andes Introduce RISC-V Co-Emulation Solution to Accelerate Chip Development
by Daniel Nenni on 12-16-2025 at 10:00 am

cover image(1)

MachineWare, and Andes Technology today announced a collaborative co-emulation solution designed to address the increasing complexity of RISC-V-based chip design. The solution integrates MachineWare’s SIM-V virtual platform, S2C’s Genesis Architect and Prodigy FPGA Prototyping Systems, and Andes’ high-performance… Read More


Aerial 5G Connectivity: Feasibility for IoT and eMBB via UAVs

Aerial 5G Connectivity: Feasibility for IoT and eMBB via UAVs
by Daniel Nenni on 12-16-2025 at 8:00 am

Alphacore Presentation Spain 2025

In the evolving landscape of telecommunications, uncrewed aerial vehicles (UAVs) are emerging as innovative platforms for extending 5G networks, particularly in areas lacking terrestrial infrastructure. Dr. Jyrki T. J. Penttinen’s paper, presented at the First International Conference on AI-enabled Unmanned … Read More


WEBINAR: Why Network-on-Chip (NoC) Has Become the Cornerstone of AI-Optimized SoCs

WEBINAR: Why Network-on-Chip (NoC) Has Become the Cornerstone of AI-Optimized SoCs
by Admin on 12-15-2025 at 8:00 am

AION Silicon Arteris Webinar

By Andy Nightingale, VP of Product Management and Marketing

As AI adoption accelerates across markets, including automotive ADAS, large-scale compute, multimedia, and edge intelligence, the foundations of system-on-chip (SoC) designs are being pushed harder than ever. Modern AI engines generate tightly coordinated, … Read More


Podcast EP322: A Wide-Ranging and Colorful Conversation with Mahesh Tirupattur

Podcast EP322: A Wide-Ranging and Colorful Conversation with Mahesh Tirupattur
by Daniel Nenni on 12-12-2025 at 10:00 am

Daniel is joined by Mahesh Tirupattur, chief executive officer at Analog Bits. Mahesh leads strategic planning to develop and implement Analog Bits’ vision and mission of enabling the silicon digital world with interfacing IP to the analog world. Additionally, Mahesh oversees all aspects of Analog Bits’ operations to ensure… Read More


CAST’s Breakthrough in Automotive IP: The MSC-CTRL Microsecond Channel Controller

CAST’s Breakthrough in Automotive IP: The MSC-CTRL Microsecond Channel Controller
by Daniel Nenni on 12-10-2025 at 2:00 pm

CAST MSC CTRL SemiWiki

In a significant advancement for automotive electronics, Semiconductor intellectual property provider CAST has unveiled the MSC-CTRL Microsecond Channel Controller IP core. This new core empowers ASIC and FPGA designers with a deterministic, microsecond-precise serial interface for connecting to smart power and sensor… Read More


Ceva-XC21 Crowned “Best IP/Processor of the Year”

Ceva-XC21 Crowned “Best IP/Processor of the Year”
by Daniel Nenni on 12-10-2025 at 8:00 am

CEVA XC21 Award Social 251125

In a resounding affirmation of innovation in semiconductor intellectual property (IP), Ceva, Inc. (NASDAQ: CEVA) has been honored with the prestigious “Best IP/Processor of the Year” award at the 2025 EE Awards Asia, held in Taipei on December 4. The accolade went to the Ceva-XC21, a groundbreaking vector digital… Read More


How PCIe Multistream Architecture Enables AI Connectivity at 64 GT/s and 128 GT/s

How PCIe Multistream Architecture Enables AI Connectivity at 64 GT/s and 128 GT/s
by Kalar Rajendiran on 12-09-2025 at 8:00 am

Link Utilization Graph

As AI and HPC systems scale to thousands of CPUs, GPUs, and accelerators, interconnect performance increasingly determines end-to-end efficiency. Training and inference pipelines rely on low-latency coordination, high-bandwidth memory transfers, and rapid communication across heterogeneous devices. With model sizes… Read More