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Disaggregating AI Compute to Break the Tokens Barrier

Disaggregating AI Compute to Break the Tokens Barrier
by Bernard Murphy on 06-10-2026 at 6:00 am

Before and after with token servers

Among several topics dominating news streams these days, giant datacenters are a leading theme. They point to an AI-centric future while raising real concerns about sustainability and scalability. Certainly land, power and water demand are very present concerns for most of us, witness growing pushback against building new… Read More


Customized Foundation IP Enables the Next Generation of Automotive Compute

Customized Foundation IP Enables the Next Generation of Automotive Compute
by Kalar Rajendiran on 06-09-2026 at 10:00 am

chip design for blog

As vehicles become increasingly software-defined, automotive semiconductor suppliers face growing pressure to deliver higher compute performance while maintaining strict requirements for power efficiency, reliability, and long-term product support. Advanced driver assistance systems (ADAS), electrification, … Read More


Rambus Delivers Complete DDR5 Client Chipset for High-Speed CUDIMM and CSODIMM Memory Modules

Rambus Delivers Complete DDR5 Client Chipset for High-Speed CUDIMM and CSODIMM Memory Modules
by Daniel Nenni on 06-09-2026 at 8:00 am

Rambus DDR5 9600 Client Memory Module Chipset

The rapid emergence of AI-enabled personal computers is driving unprecedented demand for higher memory bandwidth, improved signal integrity and greater system reliability. To address these requirements, Rambus has introduced a complete client memory interface chipset for Clocked Unbuffered Dual In-Line Memory Modules… Read More


Weebit Nano ReRAM Reaches Commercial Tape-Out Milestone

Weebit Nano ReRAM Reaches Commercial Tape-Out Milestone
by Daniel Nenni on 06-08-2026 at 6:00 am

Weebit Nano ReRAM Reaches Commercial Tape Out Milestone

Weebit Nano has achieved a critical milestone in the commercialization of Resistive Random Access Memory (ReRAM) technology with the successful tape-out of two customer products integrating its embedded non-volatile memory IP. One of the products has already returned first silicon and demonstrated functional operation,… Read More


Intel: Pushing EMIB Forward: Design Methodology Insights with Synopsys Tools

Intel: Pushing EMIB Forward: Design Methodology Insights with Synopsys Tools
by Daniel Nenni on 06-04-2026 at 6:00 am

synopsys intel linkedin update 1200x1200 v3

As advanced packaging becomes a critical enabler for next-generation semiconductor products, Intel continues to drive innovation through its Embedded Multi-die Interconnect Bridge (EMIB) technology. EMIB has emerged as a foundational packaging solution for heterogeneous integration, allowing multiple chiplets and… Read More


Why Europe Needs Its Own AI Supercomputing Platform

Why Europe Needs Its Own AI Supercomputing Platform
by Daniel Nenni on 06-02-2026 at 10:00 am

image (10)

The strategic cooperation between Semidynamics and SiPearl to develop a European sovereign rack-scale AI compute platform is important for reasons that extend far beyond technology. It represents a major step toward Europe gaining greater control over its artificial intelligence infrastructure, reducing dependence on… Read More


Breaking the Clock Lane Barrier: MIPI C-PHY/D-PHY Combo IP on TSMC N2P

Breaking the Clock Lane Barrier: MIPI C-PHY/D-PHY Combo IP on TSMC N2P
by Daniel Nenni on 06-01-2026 at 6:00 am

Mixel MIPI 2026

The transition to advanced process nodes is reshaping high-speed interface IP requirements for mobile, automotive, AR/VR, and AI edge devices. As SoC designers migrate to cutting-edge foundry technologies, the demand for highly optimized MIPI PHY solutions continues to grow. A key development in this space is the availability… Read More


CFrame60: Rewriting the Rules of Frame Compression

CFrame60: Rewriting the Rules of Frame Compression
by Daniel Nenni on 05-28-2026 at 8:00 am

CFrame60 Rewriting the Rules of Frame Compression

Chips&Media CFrame60 is a next-generation frame compression hardware IP designed to address the growing bandwidth and memory challenges in modern SoCs targeting imaging, video, AI, and display applications. Unlike conventional compression architectures that prioritize either bandwidth reduction or image quality,… Read More


SRAM compilers targeting automotive SoCs on advanced nodes

SRAM compilers targeting automotive SoCs on advanced nodes
by Don Dingee on 05-27-2026 at 6:00 am

Automotive versus consumer grade reliability

Processor IP garners the most attention in SoC design, but it’s not the only IP category begging for smart choices. Every processor core needs to be fed with data; however, frequent off-chip DRAM access incurs a large clock-cycle penalty each time. Architects now want SRAM blocks distributed throughout an SoC, putting data close… Read More


CEVA Accelerates Wireless Edge Innovation with Bluetooth HDT and Integrated RF Design Win

CEVA Accelerates Wireless Edge Innovation with Bluetooth HDT and Integrated RF Design Win
by Daniel Nenni on 05-26-2026 at 10:00 am

CEVA Accelerates Wireless Edge Innovation with Bluetooth HDT and Integrated RF Design Win

CEVA, the leading licensor of wireless connectivity and smart sensing technologies, is advancing its full-stack wireless strategy with the introduction of next-generation Bluetooth High Data Throughput (HDT) capabilities and a major integrated RF subsystem design win. The announcement underscores CEVA’s growing role… Read More