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Beyond Von Neumann: Toward a Unified Deterministic Architecture

Beyond Von Neumann: Toward a Unified Deterministic Architecture
by Admin on 09-04-2025 at 6:00 am

Beyond Von Neumann

By Thang Tran

For more than half a century, the foundations of computing have stood on a single architecture: the Von Neumann or Harvard model. Nearly all modern chips—CPUs, GPUs, and even many specialized accelerators—rely on some variant of this design. Over time, the industry has layered on complexity and specialization to… Read More


Beyond Traditional OOO: A Time-Based, Slice-Based Approach to High-Performance RISC-V CPUs

Beyond Traditional OOO: A Time-Based, Slice-Based Approach to High-Performance RISC-V CPUs
by Kalar Rajendiran on 09-01-2025 at 10:00 am

Hot Chips Logo 2025

For decades, high-performance CPU design has been dominated by traditional out-of-order (OOO) execution architectures. Giants like Intel, Arm, and AMD have refined this approach into an industry standard—balancing performance and complexity through increasingly sophisticated schedulers, speculation, and runtime … Read More


Basilisk at Hot Chips 2025 Presented Ominous Challenge to IP/EDA Status Quo

Basilisk at Hot Chips 2025 Presented Ominous Challenge to IP/EDA Status Quo
by Jonah McLeod on 08-31-2025 at 10:00 am

Hot Chips Logo 2025

At Hot Chips 2025, Philippe Sauter of ETH Zürich presented Basilisk, a project that may redefine what’s possible with open-source hardware. Basilisk is a 34 mm² RISC-V SoC fabricated at IHP Microelectronics on its open-source 130nm BiCMOS process in Germany. Basilisk, named after the Greco-Roman mythical creature known… Read More


Synopsys Enables AI Advances with UALink

Synopsys Enables AI Advances with UALink
by Mike Gianfagna on 08-28-2025 at 6:00 am

Synopsys Enables AI Advances with UALink

The evolution of hyperscale data center infrastructure to support the processing of trillions of parameters for large language models has created some rather substantial design challenges. These massive processing facilities must scale to hundreds of thousands of accelerators with highly efficient and fast connections.… Read More


Can RISC-V Help Recast the DPU Race?

Can RISC-V Help Recast the DPU Race?
by Jonah McLeod on 08-26-2025 at 10:00 am

Can RISC V Help Qualcomm

ARM’s Quiet Coup in DPUs

The datacenter is usually framed as a contest between CPUs (x86, ARM, RISC-V) and GPUs (NVIDIA, AMD, custom ASICs). But beneath those high-profile battles, another silent revolution has played out: ARM quietly displaced Intel and AMD in the Data Processing Unit (DPU) market.

DPUs — also called SmartNICs… Read More


Weebit Nano Moves into the Mainstream with Customer Adoption

Weebit Nano Moves into the Mainstream with Customer Adoption
by Mike Gianfagna on 08-20-2025 at 10:00 am

Weebit Nano Moves into the Mainstream with Customer Adoption

Disruptive technology typically follows a path of research, development, early deployment and finally commercial adoption. Each of these phases are difficult and demanding in different ways. No matter how you measure it, getting to the finish line is a significant milestone for any company. Weebit Nano is disrupting the way… Read More


Everspin CEO Sanjeev Agrawal on Why MRAM Is the Future of Memory

Everspin CEO Sanjeev Agrawal on Why MRAM Is the Future of Memory
by Admin on 08-20-2025 at 8:00 am

Toggle MRAM Everspin SemiWiki

Everspin’s recent fireside chat, moderated by Robert Blum of Lithium Partners, offered a crisp look at how the company is carving out a durable niche in non-volatile memory. CEO Sanjeev Agrawal’s core message was simple: MRAM’s mix of speed, persistence, and robustness lets it masquerade as multiple memory classes, data-logging,… Read More


Exploring the Latest Innovations in MIPI D-PHY and MIPI C-PHY

Exploring the Latest Innovations in MIPI D-PHY and MIPI C-PHY
by Daniel Nenni on 08-19-2025 at 10:00 am

MIPI Framework Mixel

The white paper “Exploring the Latest Innovations in MIPI D-PHY and MIPI C-PHY” details the latest developments in these two critical high-speed interface technologies, highlighting how they evolve to meet modern demands in camera and display systems across automotive, industrial, healthcare, and XR applications.… Read More


448G: Ready or not, here it comes!

448G: Ready or not, here it comes!
by Kalar Rajendiran on 08-19-2025 at 6:00 am

448G Host Channel Topologies Analyzed

The march toward higher-speed networking continues to be guided by the same core objectives as has always been : increase data rates, lower latency, improve reliability, reduce power consumption, and maintain or extend reach while controlling cost. For the next generation of high-speed interconnects, these requirements … Read More


S2C Advances RISC-V Ecosystem, Accelerating Innovation at 2025 Summit China

S2C Advances RISC-V Ecosystem, Accelerating Innovation at 2025 Summit China
by Daniel Nenni on 08-13-2025 at 10:00 am

pic 1 (1)

Shanghai, July 19, 2025 — S2C, a leader in functional verification, showcased its latest digital EDA solutions and key partnerships with BOSC, Xuantie, and Andes Technology at RISC-V Summit China 2025, highlighting its contributions to the ecosystem. The company also played a leading role in the EDA sub-forum, with VP Ying… Read More