Chips&Media WAVE-J is a high-performance JPEG codec intellectual property core designed for advanced imaging systems that require very large image support, high throughput, flexible pixel formats, and integrated pre- and post-processing. It succeeds the CODAJ12V architecture while retaining compatibility with … Read More
Semiconductor Intellectual Property
Quadric Extends Series C to $46 Million as Edge AI Demand Accelerates
Quadric has extended its Series C financing to $46 million through a second close led by the International Finance Corporation, the private-sector investment arm of the World Bank Group. The transaction raises Quadric’s total capital secured to approximately $90 million and strengthens its ability to commercialize programmable… Read More
Security by Design: Arteris Expands Its Partnership with Arm
Arteris has expanded its partnership with Arm to deploy Cycuity Radix hardware security assurance technology across additional next-generation Arm central processing unit (CPU) programs. The expansion follows five years of collaboration and successful use of Cycuity Radix on select Arm CPU designs, and it moves hardware… Read More
How Fast Can a Performance Model Actually Be Built?
By Thang Tran, CEO of Simplex Micro and Umesh Sisodia, CEO of CircuitSutra
Performance models have a reputation problem. They’re often treated as a long-lead, high-effort undertaking — something a design team commits to early and then waits on for months before it’s useful. The development of SimplEx Micro’s… Read More
RISC-V Advantage in Accelerator Control Highlights System Verification Challenges
When considering best-fit applications for RISC-V, the appeal of extending the instruction set and competitive pricing for storage and edge applications has been pretty clear. But I have always struggled to understand the appeal in head-on competition with Arm in premium applications such as servers and infrastructure systems.… Read More
Silicon Creations at DAC 2026: Solutions for clocking, SerDes, and sensing in 2nm (and beyond)
Silicon Creations provides world-class IP for precision and general-purpose timing (PLLs and oscillators), high-performance multi-protocol, latency optimized and protocol-specific SerDes, high-speed I/Os, and accurate VT sensors. Applications include high-performance computing for AI, smart phones, wearables,… Read More
The Architecture of Success: Why a Unified Semiconductor IP Strategy Is the Foundation of Modern SoC Design
As architects push toward advanced nodes and increasingly demanding workloads, modern silicon design has entered an era of unprecedented complexity. A single design respin can cost millions of dollars and delay market entry. Against this backdrop, designs must be balanced for performance, bandwidth, power efficiency, security… Read More
Podcast EP356: An Oveview of the Unique Skills and Broad Impact of Alphacore with Andrew Levy
Daniel is joined by Andrew Levy, Vice President of Business Development, IP & ASIC at Alphacore. Andrew leads strategic growth initiatives, customer engagement, technology commercialization, and business development activities for the company’s semiconductor IP, ASIC design services, and advanced microelectronics… Read More
WAVE-P: Hardware Acceleration for the APV Professional Video Codec
Professional video workflows demand a difficult combination of image quality, editing responsiveness, high throughput, and manageable silicon cost. Chips&Media’s WAVE-P addresses that combination as a dedicated hardware IP core for the Advanced Professional Video, or APV, codec. Designed for professional and prosumer… Read More
PCIe 7 Switch IP with Time Division Multiplexing: Powering the Next Generation of AI Connectivity
PCI Express (PCIe), PCIe switches, Time Division Multiplexing (TDM), Network Interface Cards (NICs), and SmartNICs are all well-established technologies that have formed the backbone of computing and networking systems for years. More recently, SuperNICs have emerged as the next generation of networking devices optimized… Read More

Enhancing Multi-Domain System Simulation with FMI Co-Simulation