Chips&Media CFrame60 is a next-generation frame compression hardware IP designed to address the growing bandwidth and memory challenges in modern SoCs targeting imaging, video, AI, and display applications. Unlike conventional compression architectures that prioritize either bandwidth reduction or image quality,… Read More
Semiconductor Intellectual Property
SRAM compilers targeting automotive SoCs on advanced nodes
Processor IP garners the most attention in SoC design, but it’s not the only IP category begging for smart choices. Every processor core needs to be fed with data; however, frequent off-chip DRAM access incurs a large clock-cycle penalty each time. Architects now want SRAM blocks distributed throughout an SoC, putting data close… Read More
CEVA Accelerates Wireless Edge Innovation with Bluetooth HDT and Integrated RF Design Win
CEVA, the leading licensor of wireless connectivity and smart sensing technologies, is advancing its full-stack wireless strategy with the introduction of next-generation Bluetooth High Data Throughput (HDT) capabilities and a major integrated RF subsystem design win. The announcement underscores CEVA’s growing role… Read More
What Winemakers and Chip Designers Have in Common
Consider this a standout presentation at the Silicon Catalyst Spring Portfolio Update Meeting held yesterday at the Computer History Museum. Mahesh Tirupattur, CEO of Analog Bits, is a modern-day, multidimensional semiconductor hero and one of my trusted few. Analog Bits is a premier member of the semiconductor ecosystem,… Read More
Semidynamics Secures a Strategic Investment to Advance Memory-Centric AI Inference Chips
In the rapidly evolving world of artificial intelligence hardware, memory bandwidth and data movement have become just as important as raw compute power. Addressing this challenge head-on, Semidynamics has announced a strategic investment aimed at accelerating the development of its next-generation memory-centric AI … Read More
The “New Shift-Left”: Why FPGA Prototyping is the Ultimate RISC-V IP Sandbox
In the EDA world, “Shift-Left” has traditionally been a mantra for early software development—booting the OS before the silicon even leaves the fab. But as the RISC-V revolution accelerates, the goalposts have moved. We are seeing the emergence of a “New Shift-Left”, one that focuses on critical architectural… Read More
SiFive’s P570 Gen 3 Pushes RISC-V Further Into the AI Era
With the launch of its new P570 Gen 3 processor family, SiFive is making a broader statement about the future of edge computing and the growing role of RISC-V in mainstream application processors. Rather than simply unveiling another CPU core, the company is positioning the P570 as a balanced-performance processor built specifically… Read More
Configurable xSPI memory controller IP core is FuSa-ready
SPI, invented some four decades ago, is so successful as a low-pin-count interface for microcontrollers and processor cores that it spurred memory makers to incorporate both the physical signaling interface and advanced memory command protocols into serial flash and serial pseudo-SRAM (PSRAM) devices. Those protocols, … Read More
CEO Interview with Dave Kelf, CEO of Breker Verification Systems
In the functional verification space, Breker Verification Systems stands out for its vast and long-standing understanding and ability to solve many of the seemingly intractable complexity challenges, especially in the system space.
I recently talked with Dave Kelf, Breker’s CEO, who has plenty of good news to share about Breker’s… Read More
Synopsys and TSMC Deepen AI Design Alliance: What It Means
A recent announcement from Synopsys signals a meaningful escalation in the race to build next-generation AI hardware. The expanded collaboration between Synopsys and TSMC brings together silicon-proven IP, AI-driven design tools, and cutting-edge manufacturing processes in a tightly integrated effort to accelerate high-performance… Read More


Quantum Simulation Using Decision Diagrams. Innovation in Verification