Ceva and LG Electronics have joined forces to remove one of the biggest obstacles to ultra-wideband adoption: integrating a complete radio, baseband and software stack into a production system-on-chip. Their joint platform combines Ceva-Waves UWB baseband intellectual property and software with an RF front end developed… Read More
Semiconductor Intellectual Property
PCIe 7 Switch IP with Time Division Multiplexing: Powering the Next Generation of AI Connectivity
By Tim Messegee, Senior Director of Solutions Marketing at Rambus
PCI Express (PCIe), PCIe switches, Time Division Multiplexing (TDM), Network Interface Cards (NICs), and SmartNICs are all well-established technologies that have formed the backbone of computing and networking systems for years. More recently, SuperNICs… Read More
CAST Moves the Full TCP/IP Stack into Hardware at 100 Gbps
CAST has introduced TCPIP-100G, a synthesizable intellectual-property core that implements a complete TCP/IP stack in hardware for ASICs and FPGAs. The core is designed to transmit and receive at up to 100 Gbps without depending on a host processor. That distinction is important: this is not simply a checksum engine or a network-interface… Read More
2026 Ceva Edge Symposium: Building Intelligence Beyond the Cloud
The 2026 Ceva Edge Symposium will bring together engineers, technology leaders, ecosystem partners, and innovators to explore a major shift in computing: moving artificial intelligence from distant cloud infrastructure into the devices that interact directly with the physical world. Scheduled for November 2 in Hsinchu,… Read More
Fail-Safe Frames: Why Chips&Media’s ASIL-B Video IP Matters
As vehicles evolve into software-defined, increasingly autonomous platforms, video processing is becoming part of the safety-critical computing chain. Camera feeds support functions ranging from surround-view monitoring and driver assistance to object detection and automated driving. If the hardware processing those… Read More
The $9.5 Billion Design IP Market: Shifting Boundaries, Arm’s Monopoly, and the RISC-V Response
While semiconductor design intellectual property (IP) is a $9.45 billion market, it acts as the absolute architectural bottleneck for the entire global semiconductor value chain. The choices made at the IP layer today dictate the cost, power, and security of a downstream technology economy rapidly marching toward a trillion… Read More
DAC 2026: A Discussion of Who Owns the Intelligence Behind Tomorrow’s Chips and How to Make it Better
The industry is moving from simple documentation chatbots to agentic workflows capable of performing complex, multi-step tasks like design creation, verification, and library characterization. These agents are intended to enhance engineering productivity by roughly 50%. A panel of industry experts met at DAC to discuss… Read More
RISC-V at Sixteen: From Modular ISA to Standardized Platforms at Hot Chips 2026
RISC-V has evolved from a Berkeley research architecture into a global instruction-set standard spanning embedded controllers, application processors, accelerators, and emerging servers. Its defining technical characteristic is not merely openness, but disciplined modularity. Four ratified base ISAs—RV32I, RV64I,… Read More
The Sky’s the Limit: SiFive’s BigSky Brings RISC-V to the Datacenter
SiFive is bringing RISC-V closer to mainstream datacenter deployment with the BigSky SF-2U870, an enterprise-grade development server designed for hyperscalers, semiconductor companies, software vendors, and ecosystem partners. Announced in Santa Clara on August 24, 2026, alongside Hot Chips, the rackable 2U platform… Read More
CEO Interview with Sumeet Kumar of Innatera
Dr. Sumeet Kumar is CEO of Innatera, the pioneering Dutch neuromorphic processor company. Dr. Kumar was previously with Intel and Indrion Technologies, and has spent his career in microprocessor development. He co-founded Innatera in 2018 as a spin off from the Delft University of Technology.
Tell us about your company?
When… Read More


A Study of Photoresist Bake Influence on Stochastics for DUV Immersion Lithography