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Daniel is joined by Xiaolin Chen, Senior Director of Technical Product Management for Formal Solutions at Synopsys. She has over 20 years of experience applying formal technology in verification and partnering with customers to identify opportunities where formal methods are best suited to solve complex verification challenges.… Read More
On February 3, 2026, Andes Technology officially announced the launch of RISC-V Now!, a new global conference series designed around the next phase of RISC-V adoption: real-world deployment and commercial scaling. This initiative marks a shift from exploratory and research-focused events toward practical, production-oriented… Read More
It is hard to believe this conference is older than most all of the participants, including myself. The amount of history behind this conference is amazing. Back in 1955 the meeting began as the Electron Devices Meeting (EDM), organized by what later became the IEEE Electron Devices Society. Its core purpose was to bring together… Read More
In February of 2026, Taiwan Semiconductor Manufacturing Company (TSMC) will host the TSMC AZ Exclusive Experience Day in Phoenix, Arizona, offering selected participants a rare opportunity to engage directly with one of the most advanced semiconductor manufacturing organizations in the world. The event will serve as an immersive… Read More
The Design Automation Chips to Systems Conference is the preeminent international event for professionals involved in electronic design, system architecture, and EDA. Formerly known simply as the Design Automation Conference or DAC has evolved over more than six decades into a forward-looking forum that spans the entire… Read More
The rapid growth of signal processing workloads in embedded, mobile, and edge computing systems has intensified the need for efficient, low-latency computation. Rich Fuhler’s update on the RISC-V Packed SIMD extension highlights why scalar SIMD digital signal processing (DSP) instructions are becoming a critical architectural… Read More
Verification has become the dominant bottleneck in modern chip design. As much as 70% of the overall design cycle is now spent on verification, a figure driven upward by increasing design complexity, compressed schedules, and a chronic shortage of design verification (DV) engineering bandwidth. Modern chips generate thousands… Read More
By Frank Schirrmeister, Synopsys
Disclaimer: This article is written in my role as Engineering Track Chair for DAC 2026
If you’ve ever walked out of DAC with a handful of practical ideas you could put to work when you return to work, you already know the value of the Engineering Track. It’s where practitioners talk to practitioners… Read More
I just completed the annual Rapha 500 Challenge on Strava by cycling 869 km in eight days, so it’s time to give you my annual recap of CES 2026 and all things cycling. Similar to previous years the big push again in 2026 are e-bikes and even e-motos. The AI acronym was everywhere too in product names and announcements as physical… Read More
Daniel is joined by Jorn Smeets, Managing Director for North America at PhotonDelta, an industry accelerator for photonic chip technology. Based in Silicon Valley, his mission is to advance the photonic chip industry by fostering collaboration between European and North American entities.
Dan explores the focus of PhotonDelta… Read More
Advancing Automotive Memory: Development of an 8nm 128Mb Embedded STT-MRAM with Sub-ppm Reliability