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The 2025 Design and Verification Conference (DVCon) was a four-day event packed with insightful discussions, cutting-edge technology showcases, and thought-provoking debates. The conference agenda included a rich mix of tutorial sessions, a keynote presentation, a panel discussion, and an exhibit hall with Electronic… Read More
Last week, Synopsys announced an expansion of their Hardware-Assisted Verification (HAV) portfolio to accelerate semiconductor design innovations. These advancements are designed to meet the increasing demands of semiconductor complexity, enabling faster and more efficient verification across software and hardware… Read More
Artificial intelligence and machine learning have undergone incredible changes over the past decade or so. We’ve witnessed the rise of convolutional neural networks and recurrent neural networks. More recently, the rise of generative AI and transformers. At every step, accuracy has been improved as depicted in the graphic… Read More
Multi-die design has become the center of a lot of conversation lately. The ability to integrate multiple heterogeneous devices into a single package has changed the semiconductor landscape, permanently. This technology has opened a path for continued Moore’s Law scaling at the system level. What comes next will truly be exciting.… Read More
Predictions in technology adoption often hinge on a delicate balance between technical feasibility and market dynamics. While business considerations play a pivotal role, the technical category reasons for the success or failure of a prediction are more tangible and often easier to identify—if scrutinized with care. However,… Read More
Part 2 of 2 – Performance Validation Across Hardware Blocks and Firmware in SoC Designs
Part 2 explores the performance validation process across hardware blocks and firmware in System-on-Chip (SoC) designs, emphasizing the critical role of Hardware-Assisted Verification (HAV) platforms. It outlines the validation workflow… Read More
Part 1 of 2 – Essential Performance Metrics to Validate SoC Performance Analysis
Part 1 provides an overview of the key performance metrics across three foundational blocks of System-on-Chip (SoC) designs that are vital for success in the rapidly evolving semiconductor industry and presents a holistic approach to optimize… Read More
There is ample evidence that technologies such as high-performance computing, next-generation servers, and AI accelerators are fueling unprecedented demands in data processing speed with massive data storage, lower latency, and lower power. Heterogeneous system integration, more commonly called 2.5 and 3D IC design, … Read More
As industries become more reliant on advanced technologies, the importance of ensuring the reliability and longevity of critical systems grows. Failures in components, whether in autonomous vehicles, high performance computing (HPC), healthcare devices, or industrial automation, can have far-reaching consequences.… Read More
2.5D and 3D multi-die design is rapidly moving into the mainstream for many applications. HPC, GPU, mobile, and AI/ML are application areas that have seen real benefits. The concept of “mix/match” for chips and chiplets to form a complex system sounds deceptively simple. In fact, the implementation and analysis techniques required… Read More
Podcast EP219: How Synopsys Addresses Debug and Coverage Closure Challenges with Robert Ruiz
Podcast EP188: The New Demands for Memory Design and the Synopsys Approach with Anand Thiruvengadam
Podcast EP185: DRAM Scaling, From Atoms to Circuits with Synopsys’ Dr. Victor Moroz
Podcast EP178: An Overview of Advanced Power Optimization at Synopsys with William Ruby
Podcast EP169: How Are the Standards for the Terabit Era Defined?
Podcast EP152: An Informal Conversation with Aart de Geus on AI and Multi-Die at SNUG
Podcast EP148: The Synopsys View of High-Performance Communication and the Role of Chiplets
Podcast EP141: The Role of Synopsys High-Speed SerDes for Future Ethernet Applications
Podcast EP240: Challenges and Strategies to Address New Embedded Memory Architectures with Mark Han
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