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EDA

Electronic Design Automation

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Clock Domain Crossing, a potted history

Clock Domain Crossing, a potted history
by Paul McLellan on 03-03-2011 at 11:23 am
Categories: EDA

Yesterday I talked to Shaker Sarwary, the senior product director for Atrenta’s clock-domain crossing (CDC) product SpyGlass-CDC. I asked him how it came about. The product was originally started nearly 8 years ago, around the time Atrenta itself got going. Shaker got involved about 5 years ago.

Originally this was a small… Read More

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Semiconductor Power Crisis and TSMC!

Semiconductor Power Crisis and TSMC!
by Daniel Nenni on 03-02-2011 at 8:48 pm
Categories: EDA, Foundries, TSMC

Power grids all over the world are already overloaded even without the slew of new electronic gadgets and cars coming out this year. At ISSCC, Dr. Jack Sun, TSMC Vice President of R&D and Chief Technology Officer made the comparison of a human brain to the closest thing available in silicon, a graphical processing unit (GPU).… Read More

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With EUVL, Expect No Holiday

With EUVL, Expect No Holiday
by Beth Martin on 03-02-2011 at 1:12 pm
Categories: EDA, Siemens EDA

For a brief time in the 1990s, when 4X magnification steppers suddenly made mask features 4X larger, there was a period in the industry referred to as the “mask vendor’s holiday.” The party ended before it got started with the arrival of sub-wavelength lithography, and we all trudged back to the OPC/RET mines. Since then, the demands… Read More

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Intel Sandy Bridge Fiasco and EDA

Intel Sandy Bridge Fiasco and EDA
by Daniel Nenni on 02-27-2011 at 6:49 am
Categories: EDA, Foundries, Intel

I purchased two Toyotas last year and both have since been recalled. Why has Toyota spent $1B+ on recalls in recent years? Same reason why it will cost Intel $700M (which does not include reputation damage) to recall Sandy Bridge chip sets, because someone did not do their job! The WHAT has been discussed, lets talk about HOW it happened.… Read More

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Wally Rhines DvCon 2011 Ketnote: From Volume to Velocity

Wally Rhines DvCon 2011 Ketnote: From Volume to Velocity
by Daniel Nenni on 02-23-2011 at 1:49 pm
Categories: EDA, Siemens EDA

Abstract:
There has been a remarkable acceleration in the adoption of advanced verification methodologies, languages and new standards. This is true across all types of IC design and geographic regions. Designers and verification engineers are surprisingly open to new approaches to keep pace with the relentless rise in design… Read More

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Evolution of process models, part I

Evolution of process models, part I
by Beth Martin on 02-23-2011 at 1:15 pm
Categories: EDA, Siemens EDA

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Thirty five years ago, in 1976, the Concorde cut transatlantic flying time to 3.5 hrs, Apple was formed, NASA unveiled the first space shuttle, the VHS vs Betamax wars started, and Barry Manilow’s I Write the Songs saturated the airwaves. Each of those advances, except perhaps Barry Manilow, was the result of the first modern-era,… Read More

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Custom and AMS Design

Custom and AMS Design
by Daniel Payne on 02-21-2011 at 10:06 pm
Categories: EDA, Foundries, TSMC

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For IC designers creating full-custom or AMS designs there are plenty of challenges to getting designs done right on the first spin of silicon. Let me give you a sneak peek into what’s being discussed at the EDA Tech Forum in Santa Clara, CA on March 10th that will be of special interest to you:

3D TSV (Through Silicon Vias) are… Read More

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Synopsys at Goldman Sachs Technology Conference

Synopsys at Goldman Sachs Technology Conference
by Paul McLellan on 02-21-2011 at 7:00 pm
Categories: EDA, Synopsys

Aart de Geus was interviewed at the Goldman Sachs Technology Conference last week. Here is some of what he said. Strong Q1, good Q2 outlook, on-track for 2011 guidance. Strong rebound in Far East, Europe mixed, North America good. 80% revenue for year booked by start of year, 90% revenue for a quarter already booked at start of quarter.… Read More

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Clock Domain Crossing (CDC) Verification

Clock Domain Crossing (CDC) Verification
by Paul McLellan on 02-21-2011 at 6:12 pm
Categories: EDA

Multiple, independent clocks are quintessential in SoCs and other complex ASICs today. In some cases, such as in large communications processors, clock domains may number in the hundreds. Clock domain crossings pose a growing challenge to chip designers, and constitute a major source of design errors–errors that can… Read More

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Mentor Graphics Should Be Acquired or Sold: Carl Icahn COUNTERPOINT

Mentor Graphics Should Be Acquired or Sold: Carl Icahn COUNTERPOINT
by Daniel Nenni on 02-20-2011 at 7:04 pm
Categories: EDA


Daniel,

On Jan 20th, you criticized that the EDA models are all broken and need to change. Ridiculing Synpsys, Cadence, Mentor and Magma for not agreeing to ‘pay for success’ type of model (some form of royalties).

On Feb 14th, you state thatIcahn doesn’t understand EDA and should stay out. Maybe he is seeing … Read More