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Jasper Property Synthesis Apps

Jasper Property Synthesis Apps
by Paul McLellan on 10-29-2012 at 7:00 am

Jasper restructured JasperGold so that it could deliver its formal technology more flexibly by having a base system and a porfolio of apps. This would also make it easier to upgrade capabilities by creating new apps. Today, Jasper announced two new apps:

  • JasperGold Structural Property Synthesis (SPS)
  • JasperGold Behavioral
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An AMS Reference Flow for Power Management Designs

An AMS Reference Flow for Power Management Designs
by Daniel Payne on 10-26-2012 at 5:42 pm

At DAC in June I visited and blogged about 30+ EDA and Semi IP companies, however I didn’t have time to watch the TowerJazz presentation in the Cadence Theater entitled: AMS Flow for Power Management Designs. Today I watched the 26 minute video and have summarized what I learned in this blog post.… Read More


Simulation: Expert Insights into Modeling Microcontrollers @ Renesas DevCon

Simulation: Expert Insights into Modeling Microcontrollers @ Renesas DevCon
by Holly Stump on 10-25-2012 at 9:03 pm

Simulation: Expert Insights into Modeling Microcontrollers” was the recent panel hot topic at Renesas DevCon2012, featuring Paolo Giustoof GM, Mark Ramseyerof Renesas, Marc Serughettiof Synopsys, Jay Yantchevof ASTC / VWorks, and Simon Davidmannof Imperas.
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SoC emulation syncs up with SuperSpeed USB

SoC emulation syncs up with SuperSpeed USB
by Don Dingee on 10-25-2012 at 9:00 pm

They say what adds value is to take something difficult and make it look simple. USB looks so simple when it is done right, but designers know it can be one of the more tempermental features in an SoC, especially in the latest SuperSpeed incarnation.… Read More


Brian Bailey Interviews Kathryn Kranen

Brian Bailey Interviews Kathryn Kranen
by Paul McLellan on 10-25-2012 at 6:23 pm

Brian Bailey at EETimes has an interesting interview with Kathryn Kranen. He says that the interview will be published in installments but the first one is up here. This first installment is mostly about how long-lived EDA companies (and others) have become since it takes a long time to build up enough revenue to be able to IPO.

She… Read More


Model Driven Development

Model Driven Development
by Paul McLellan on 10-25-2012 at 5:50 pm

Mentor has a webinar on Model Driven Development (MDD) for Systems Engineering, presented by Bill Chown. It is actually the first of 15 webinars. This first one is just over 30 minutes long and I assume the others will be too. The webinar focuses on embedded system development, which historically has largely been validated using… Read More


A Brief History of Semiconductors

A Brief History of Semiconductors
by Paul McLellan on 10-25-2012 at 3:00 pm

In the last few decades, electronics has become more and more central to our lives. When I was a child the only electronics in the house was the radio and the television, both of which contained tubes. Two big things happened that upended that world: the invention of the transistor and the invention of the integrated circuit. A modern… Read More


CDNLive Call For Papers

CDNLive Call For Papers
by Paul McLellan on 10-24-2012 at 6:44 pm

The Silicon Valley CDNLive, the Cadence user conference, will be on March 12-13th 2013 in Santa Clara. But the heart of CDNLive are customer presentations and the call for papers is now open. The deadline is December 4th (at 5pm PST for people who really like to come down to the wire). At this point only an abstract is required.

There… Read More


The Auto Industry Speaks @ Renesas DevCon

The Auto Industry Speaks @ Renesas DevCon
by Holly Stump on 10-23-2012 at 9:00 pm


This year’s Renesas DevCon in Orange County, CA kicked off yesterday with an impressive lineup of speakers, record attendance, and an increased focus on automotive.

TheAuto Industry Speaks,” an Expert Panel organized by Martin Bakerof Renesas, featured:

  • Yoichi Yano, RenesasExecutive VP and Member of the Board, who early
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Power and Reliability Challenges

Power and Reliability Challenges
by Paul McLellan on 10-23-2012 at 12:38 pm

Last week I attended the Ansys/Apache seminars on “Dimensions of Electronic Design.” The two big challenges as we go down to 28nm and 20nm and below are keeping power manageable and keeping reliability up.

The big challenge with power is that we can put so much stuff on a die and clock it so fast that the power is exceeding… Read More