SiC 800 2026ChipletSummit Static (1)
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EDA

Electronic Design Automation

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EDA User: Rafaela Novais from TowerJazz Semi

EDA User: Rafaela Novais from TowerJazz Semi
by Daniel Payne on 10-04-2012 at 8:10 pm
Categories: Cliosoft, EDA
2 Comments

While reading an article on DeepChip I found an interesting comment from Rafaela Novais, a Design Support Manager at TowerJazz Semi and decided to interview her to learn more about her experience as an IC designer and EDA tool user.

… Read More

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EDA Solutions at Ultra Low Power Developer Forum Demonstrates Mixed-Signal Flow including Tools from Tanner EDA, Incentia and Aldec

EDA Solutions at Ultra Low Power Developer Forum Demonstrates Mixed-Signal Flow including Tools from Tanner EDA, Incentia and Aldec
by Daniel Payne on 10-04-2012 at 4:49 pm
Categories: Aldec, EDA, Tanner EDA

EDA Solutions, sole representative in Europe for Tanner EDA and Incentia Design Systems, is exhibiting at the ‘Design & Elektronik’ Developer Forum on Ultra Low Power in Munich, Germany, on October 10, 2012, at the Holiday Inn (Munich – City Centre).

EDA Solutions will be presenting its complete analog, digital and… Read More

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New MIPI protocols: Unipro, LLI and CSI3 over MPHY.

New MIPI protocols: Unipro, LLI and CSI3 over MPHY.
by Eric Esteve on 10-04-2012 at 8:10 am
Categories: Cadence, IP

New MIPI protocols: Unipro, LLI and CSI3 over MPHY.

Gabriele ZARRI, Moshik RUBIN, Cadence
Sophia Antipolis, France SAME 2012 Conference – October 2 & 3, 2012 2

Abstract:

With more than 50% of the world‟s population using cellular phones and the growing number of devices that go mobile, from game consoles and media player… Read More

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High Frequency Analysis of IC Layouts

High Frequency Analysis of IC Layouts
by Daniel Payne on 10-03-2012 at 12:26 pm
Categories: EDA, Siemens EDA

IC designers of passive devices often use empirical approaches to perform High Frequency Analysis (HFA), however there is at least one new approach being offered by Mentor Graphics using a tool flow of:

… Read More
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Dimensions of Electronic Design Seminars

Dimensions of Electronic Design Seminars
by Paul McLellan on 10-02-2012 at 6:37 pm
Categories: Ansys, Inc., EDA

ANSYS and Apache are putting on a new series of seminars about designing future electronic systems. These are only getting more complex, of course, cramming more and more functionality into smaller portable devices with good battery life (and not getting too hot), integrating multiple antennas into a single platform, and TSV-based… Read More

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Cooley on Synopsys-EVE

Cooley on Synopsys-EVE
by Paul McLellan on 10-02-2012 at 7:56 am
Categories: EDA, Synopsys
9 Comments

John Cooley has an interesting “scoop” on the Synopsys-EVE acquisition. The acquisition itself is not a surprise, it is the one big hole in Synopsys’s product line and EVE is the perfect plug to fill it. It was also about the only thing Cadence has (apart from PCB) that Synopsys does not.

The interesting thing … Read More

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Converge in Detroit

Converge in Detroit
by Paul McLellan on 09-30-2012 at 10:04 pm
Categories: EDA, Synopsys

When I worked for VaST we went to a show that I’d never heard of in EDA: SAE Convergence (SAE is the Society of Automotive Engineers). It is held once every two years and it focuses on transportation electronics, primarily automotive although there did seem to be some aerospace stuff there too. This is an even year, Convergence… Read More

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Variation at 28-nm with Solido and GLOBALFOUNDRIES

Variation at 28-nm with Solido and GLOBALFOUNDRIES
by Kris Breen on 09-27-2012 at 9:00 pm
Categories: EDA, Foundries, GlobalFoundries, Solido
1 Comment

At DAC 2012 GLOBALFOUNDRIES and Solido presented a user track poster titled “Understanding and Designing for Variation in GLOBALFOUNDRIES 28-nm Technology” (as was previously announced here). This post describes the work that we presented.

We set out to better understand the effects of variation on design at 28-nm. In particular,… Read More

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A Brief History of RTL Design

A Brief History of RTL Design
by Daniel Payne on 09-27-2012 at 9:00 pm
Categories: EDA
7 Comments

300px Register transfer level example toggler.svg

RTL is an acronym for Register Transfer Level and refers to a level of hardware design abstraction using Registers and logic gates. Here’s an example schematic showing one DFF as a register, and one inverter as a logic gate.


Figure 1: RTL diagram of a DFF (D Flip Flop) and Inverter… Read More