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Electronic Design Automation
We have talked about fault localization (root cause analysis) in several reviews. This early-release paper looks at applying LLM technology to the task. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research… Read More
All aspects of semiconductor design and manufacturing require collaboration across a global ecosystem. As complexity increases, so does the importance of good collaboration. This is especially true for advanced package design. Thanks to the movement to multi-die design, package development has become an incredibly difficult… Read More
Twenty-five years ago, SEMATECH first alerted the world to a concern known as the design productivity gap: the observation that the ability to manufacture complex chips had started outpacing the capability of designers to create them by more than a factor of two. This concern was subsequently reiterated… Read More
Git is a version control system that saves every change made to files. It offers powerful tools for managing these changes. This makes Git ideal for software development, as it lets you keep all project files in one place.
Software has grown in complexity, necessitating more collaboration among engineers across various time zones.… Read More
I’m guessing that more than a few people were mystified (maybe still are) when Cadence acquired OpenEye Scientific, a company known for computational molecular design aimed at medical drug/therapeutics discovery. What could EDA, even SDA (system design automation), and drug discovery possibly have in common? More than you… Read More
AI and ML techniques are popular topics, yet there are considerable challenges to those that want to design and build an AI accelerator for inferencing, as you need a team that understands how to model a neural network in a language like Python, turn that model into RTL, then verify that your RTL matches Python. Researchers from CERN,… Read More
Sirius Wireless partnered with FPGA prototyping expert S2C to develop the Wi-Fi 7 RF IP Verification System, enhancing working efficiency and accelerating time-to-market for clients.
Wi-Fi 7 is the latest Wi-Fi technology, with speeds of up to 30Gbps, approximately three times the peak performance of Wi-Fi 6. This enhanced… Read More
Most of us are familiar with the metastability problems that can be caused by clock domain crossings (CDC). Early static analysis techniques can flag these kinds of issues to ensure there are no surprises later. I spent quite a bit of time at Atrenta, the SpyGlass company, so I am very familiar with these challenges. Due to the demands… Read More
Around the mid-2000’s the performance component of Moore’s Law started to tail off. That slack was nicely picked up by architecture improvements which continue to march forward but add a new layer of complexity in performance optimization and verification. Nick Heaton (Distinguished Engineer and Verification Architect at… Read More
We all know that making advanced semiconductors is a team sport. TSMC can innovate the best processes, but without the right design flows, communication schemes and verified IP it becomes difficult to access those processes. Synopsys recently announced some details on this topic. It covers a lot of ground. The graphic at the top… Read More
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