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Electronic Design Automation
Logic equivalence checking (LEC) is an automated process to verify that modified versions of a design evolving through implementation remain logically equivalent to the functionally signed-off RTL. This becomes important when accounting for retiming optimizations and for necessary implementation-stage ECOs which must… Read More
Visiting a new EDA vendor at #61DAC is always a treat, because much innovation comes from the start-up companies, instead of the established big four EDA companies. I met with Vincent Bligny, Founder and CEO of Aniah on Wednesday in their booth, to hear about what they are doing differently in EDA. Mr. Bligny has a background working… Read More
As a technical marketing consultant, I always enjoy the chance to talk to hands-on users of my clients’ electronic design automation (EDA) tools to “see how the sausage is made” on actual projects. Cristian Amitroaie, CEO of AMIQ EDA, recently connected me with Verification and Infrastructure Manager Dan Cohen and Verification… Read More
During a recent LinkedIn webcast, Dr. Ian Cutress, Chief Analyst at More than Moore and Host at TechTechPotato, and Priyank Shukla, Principal Product Manager at Synopsys, shared their thoughts regarding the industry drivers, design considerations, and critical advancements in compute interconnects enabling data center… Read More
The integration of artificial intelligence (AI) into Electronic Design Automation (EDA) is revolutionizing chip design, addressing the critical shortage of skilled engineers and accelerating the development process. As Jeff Dyck, Senior Director of Engineering at Siemens EDA, explains in a recent DACtv presentation, … Read More
In a DACtv session on July 22, 2024, Rich Goldman from Ansys discussed the partnership with NVIDIA, focusing on accelerating engineering simulations and visualizing 3D IC designs in Omniverse. The collaboration, outlined in six pillars defined by NVIDIA CEO Jensen Huang, leverages NVIDIA’s GPUs and Grace CPUs to enhance… Read More
I first visited Easy-Logic at DAC in 2023, so it was time to meet them again at #61DAC in San Francisco to find out what’s new this year. Steven Chen, VP Sales for North America and Asia met with me in their booth for an update briefing. Steven has been with Easy-Logic for six years now and earned an MBA from Baruch College in New York. This… Read More
At #61DAC I stopped by the Defacto Technologies exhibit and talked with Chouki Aktouf, President and CEO, to find out what’s new in 2024. ARM and Defacto have a joint SoC design flow by using the Arm IP Explorer tool along with Defacto’s SoC compiler, which helps to quickly create your top-level RTL, IP-XACT and UPF files. This tool… Read More
An explosion in multiplier types/combinations lacking well-established C reference models for equivalence checking is prompting a closer look at theorem proving methods for verification. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco… Read More
I stopped by the AMIQ EDA booth at DAC to get an update from Tom Anderson about their Integrated Development Environment (IDE), aimed at helping design and verification engineers save time. In my early IC design days we used either vi or emacs and were happy with having a somewhat smart text editor. With an IDE you get a whole new way … Read More
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The AI PC: A New Category Poised to Reignite the PC Market