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EDA

Electronic Design Automation

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3D TCAD Simulation of Silicon Power Devices

3D TCAD Simulation of Silicon Power Devices
by Daniel Payne on 04-07-2016 at 12:00 pm
Categories: EDA, FinFET

Process and device engineers are some of the unsung heroes in our semiconductor industry that have the daunting task of figuring out how to actually create a new process node that will fit some specific, market niche with sufficient yield to make their companies profitable and stand out from the competition. One such market segment… Read More

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The Most Important Point You May Have Missed at CDNLive 2016!

The Most Important Point You May Have Missed at CDNLive 2016!
by Daniel Nenni on 04-06-2016 at 4:00 am
Categories: Cadence, EDA

This was the best keynote lineup I can remember at a user group meeting. All four speakers are visionaries but from very different perspectives. The video of the event will be up later this month but from my first count the word “System(s)” was mentioned 32 times and the underlying message will transform the semiconductor industry… Read More

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Innovation in Transistor Design with Carbon Nanotubes

Innovation in Transistor Design with Carbon Nanotubes
by Students@olemiss.edu on 04-05-2016 at 4:00 pm
Categories: EDA

The New York Times article “IBM Scientists Find New Way to Shrink Transistors” by John Markoff focuses on the goal of the semiconductor industry to create smaller transistors in order to remain competitive while emphasizing cutting-edge design strategies with the use of carbon nanotubes. By switching from traditional methods… Read More

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Analog Design Verification — Traceability is Required

Analog Design Verification — Traceability is Required
by Tom Dillinger on 04-05-2016 at 9:45 am
Categories: Cadence, EDA

Digital verification engineers have developed robust, thorough metrics for evaluating design coverage. Numerous tools are available to evaluate testbenches against RTL model descriptions — e.g., confirming that simulation regressions exhaustively exercise signal toggles, RTL statement lines, individual statement… Read More

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PCB Design Requires Both Speed and Accuracy of SI/PI Analysis

PCB Design Requires Both Speed and Accuracy of SI/PI Analysis
by Tom Dillinger on 04-04-2016 at 8:00 am
Categories: EDA, Siemens EDA

The prevailing industry trends are clear: (1) PCB and die package designs are becoming more complex, across both mobile and high-performance applications; (2) communication interface performance between chips (and their related protocols) is increasingly demanding to verify; (3) signal integrity and power integrity issues… Read More

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CMOS Radio Frequency Image Sensor Process

CMOS Radio Frequency Image Sensor Process
by Students@olemiss.edu on 04-03-2016 at 4:00 pm
Categories: EDA

Image censoring with radio frequency (RF) in CMOS is a combination of light sensing chips and wireless communication. Typically, we were first engaged in the article, “RF Design Issues and Challenges in a CMOS Image Sensor Process”, because of the circuit design process required to make a functioning Radio Frequency transceiver.… Read More

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Managing and Reusing IP in a Build-Borrow-Buy Era

Managing and Reusing IP in a Build-Borrow-Buy Era
by Don Dingee on 04-01-2016 at 4:00 pm
Categories: Cliosoft, EDA

Make-versus-buy inadequately describes what we do now in electronic systems design. We are on a continuum of design IP acquisition and use decisions, often with a portfolio of active projects and future projects depending on the outcome. Properly managing IP means adopting a build-borrow-buy mindset and tools capable of handling… Read More

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IoT or Smart Everything?

IoT or Smart Everything?
by Daniel Payne on 03-31-2016 at 12:00 pm
Categories: IoT, Synopsys

I just attended a keynote presentation at SNUG from Aart de Geus, CEO of Synopsys. This event is well attended with some 2,500 people that are learning from the 96 presentations on all things Synopsys, semiconductor. IP, and foundry trends. There are big name sponsors like: GLOBALFOUNDRIES, Samsung, socioeconomic, TSMC, Fujitsu,… Read More

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The Latest in Static Timing Analysis with Variation Modeling

The Latest in Static Timing Analysis with Variation Modeling
by Tom Dillinger on 03-30-2016 at 12:00 pm
Categories: Cadence, EDA

In many ways, static timing analysis (STA) is more of an art than a science. Methodologists are faced with addressing complex phenomena that impact circuit delay — e.g., signal crosstalk, dynamic I*R supply voltage drop, temperature inversion, device aging effects, and especially (correlated and uncorrelated) process… Read More