Custom and analog/mixed-signal IC designs have some unique IP and symmetry checking requirements for physical design. Waiting until the end of the IC layout process to verify IP instances for correctness or proper symmetry will cause project delays, so an approach to perform earlier physical verification makes more sense. … Read More
Electronic Design Automation
S2C: Empowering Smarter Futures with Arm-Based Solutions
The tech world is sprinting toward a future where your fridge orders groceries, your car avoids traffic before you hit it, and security cameras don’t just watch—they understand. But behind these innovations lies a messy truth: building the brains for these smart systems is complicated.
Fresh off the 2024 Arm Tech Symposia… Read More
DVCon 2025: AI and the Future of Verification Take Center Stage
The 2025 Design and Verification Conference (DVCon) was a four-day event packed with insightful discussions, cutting-edge technology showcases, and thought-provoking debates. The conference agenda included a rich mix of tutorial sessions, a keynote presentation, a panel discussion, and an exhibit hall with Electronic… Read More
AlphaDesign AI Experts Wade into Design and Verification
I mentioned in an earlier blog that multiple presentations at DVCon 2025 went all-in on AI-assisted design and verification. The presentation was one such example, looking very much at top-down AI-expert application of agentic flows to design and verification. AlphaDesign is a new startup out of UC Santa Barbara headed by William… Read More
An Imaginative Approach to AI-based Design
DVCon 2025 was unquestionably a forum for pulling out all the stops in AI-based (RTL) design and verification, particularly around generative AI and agentic methods. I heard three product pitches and a keynote and have been told that every AI talk was standing room only. A pitch from Rise-DA particularly appealed to me because … Read More
Unlocking the cloud: A new era for post-tapeout flow for semiconductor manufacturing
As semiconductor chips shrink and design complexity skyrockets, managing post-tapeout flow (PTOF) jobs has become one of the most compute-intensive tasks in manufacturing. Advanced computational lithography demands an enormous amount of computing power, putting traditional in-house resources to the test. Enter the … Read More
SemiWiki Outlook 2025 with yieldHUB Founder & CEO John O’Donnell
What was the most exciting high point of 2024 for your company?
One of the most exciting milestones in 2024 was the further expansion of our data science team, which allowed us to take a bold step toward fully integrating AI into our solutions. This not only is enhancing our offerings but also helped us grow within our existing customer… Read More
TRNG for Automotive achieves ISO 26262 and ISO/SAE 21434 compliance
The security of a device or system depends mainly on being unable to infer or guess an alphanumeric code needed to gain access to it or its data, be that a password or an encryption key. In automotive applications, the security requirement goes one step further – an attacker may not gain access per se, but if they can compromise vehicle… Read More
Bug Hunting in Multi Core Processors. Innovation in Verification
What’s new in debugging multi-/many-core systems? Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A) and I continue our series on research ideas. As always, feedback welcome.
The Innovation
This month’s pick is Post-Silicon… Read More
Synopsys Expands Hardware-Assisted Verification Portfolio to Address Growing Chip Complexity
Last week, Synopsys announced an expansion of their Hardware-Assisted Verification (HAV) portfolio to accelerate semiconductor design innovations. These advancements are designed to meet the increasing demands of semiconductor complexity, enabling faster and more efficient verification across software and hardware… Read More
Rapidus, IBM, and the Billion-Dollar Silicon Sovereignty Bet