Banner Electrical Verification The invisible bottleneck in IC design updated 1
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Hierarchically defining bump and pin regions overcomes 3D IC complexity

Hierarchically defining bump and pin regions overcomes 3D IC complexity
by Admin on 11-13-2025 at 8:00 am

connectivity in a hierarchical IC package floorplan

By Todd Burkholder and Per Viklund, Siemens EDA

The landscape of advanced IC packaging is rapidly evolving, driven by the imperative to support innovation on increasingly complex and high-capacity products. The broad industry trend toward heterogeneous integration of diverse die and chiplets into advanced semiconductor… Read More


CEO Interview with Rodrigo Jaramillo of Circuify Semiconductors

CEO Interview with Rodrigo Jaramillo of Circuify Semiconductors
by Daniel Nenni on 11-01-2025 at 8:00 am

Rodrigo Jaramillo CEO, Circuify Semiconductors Nov 2025

With over 18 years of experience in the semiconductor industry, Rodrigo Jaramillo is the Co-Founder and CEO of Circuify Semiconductors, an engineering design solutions startup based in Guadalajara, Mexico. Circuify provides ASIC, SoC, and Chiplet design services for the North American semiconductor industry, with experience… Read More


Podcast EP315: The Journey to Multi-Die and Chiplet Design with Robert Kruger of Synopsys

Podcast EP315: The Journey to Multi-Die and Chiplet Design with Robert Kruger of Synopsys
by Daniel Nenni on 10-31-2025 at 10:00 am

Daniel is joined by Robert Kruger, product management director at Synopsys, where he oversees IP solutions for multi-die designs, including 2D, 3D, and 3.5D topologies. Throughout his career, Robert has held key roles in product marketing, business development, and roadmap planning at leading companies such as Intel, Broadcom,… Read More


Podcast EP313: How proteanTecs Optimizes Production Test

Podcast EP313: How proteanTecs Optimizes Production Test
by Daniel Nenni on 10-24-2025 at 10:00 am

Daniel is joined by Alex Burlak is Vice President of Test & Analytics at proteanTecs. With combined expertise in production testing and data analytics of ICs and system products, Alex joined proteanTecs in October, 2018. Before joining the company, Alex held a Senior Director of Interconnect and Silicon Photonics Product… Read More


Chiplets: Powering the Next Generation of AI Systems

Chiplets: Powering the Next Generation of AI Systems
by Kalar Rajendiran on 10-23-2025 at 10:00 am

Arm Synopsys at Chiplet Summit

AI’s rapid expansion is reshaping semiconductor design. The compute and I/O needs of modern AI workloads have outgrown what traditional SoC scaling can deliver. As monolithic dies approach reticle limits, yields drop and costs rise, while analog and I/O circuits gain little from moving to advanced process nodes. To sustain … Read More


Podcast EP312: Approaches to Advance the Use of Non-Volatile Embedded Memory with Dave Eggleston

Podcast EP312: Approaches to Advance the Use of Non-Volatile Embedded Memory with Dave Eggleston
by Daniel Nenni on 10-22-2025 at 8:00 am

Daniel is joined by Dave Eggleston is senior business development manager at Microchip with a focus on licensing SST SuperFlash technology. Dave’s extensive background in Flash, MRAM, RRAM, and storage is built on 30+ years of industry experience. This includes serving as VP of Embedded Memory at GLOBALFOUNDRIES, CEO… Read More


Exploring TSMC’s OIP Ecosystem Benefits

Exploring TSMC’s OIP Ecosystem Benefits
by Daniel Nenni on 10-10-2025 at 6:00 am

TSMC Booth

Now that the dust has settled let’s talk more about TSMC’s Open Innovation Platform. Launched in 2008, OIP represents a groundbreaking collaborative model in the semiconductor industry. Unlike IDMs that controlled the entire supply chain, OIP fosters an “open horizontal” ecosystem uniting TSMC… Read More


GlobalFoundries, MIPS, and the Chiplet Race for AI Datacenters

GlobalFoundries, MIPS, and the Chiplet Race for AI Datacenters
by Jonah McLeod on 10-09-2025 at 6:00 am

GF MIPS

GlobalFoundries’ (GF) acquisition of MIPS in 2025 wasn’t a nostalgic move to revive a legacy CPU brand. It was a calculated step into one of the most lucrative frontiers in semiconductors: AI, high-performance computing (HPC), and datacenters. As Nvidia, AMD, Intel, and hyperscalers embrace chiplet architectures, GF is betting… Read More


Teradyne and TSMC: Pioneering the Future of Semiconductor Testing Through the 2025 OIP Partner of the Year Award

Teradyne and TSMC: Pioneering the Future of Semiconductor Testing Through the 2025 OIP Partner of the Year Award
by Daniel Nenni on 10-06-2025 at 10:00 am

TSMC 3D Fabric Packaging TSMC OIP 2025

In a significant milestone for the semiconductor industry, Teradyne was honored as the 2025 TSMC Open Innovation Platform® Partner of the Year for TSMC 3DFabric® Testing. This award, announced on September 25, 2025, underscores the deep collaboration between Teradyne, a leader in automated test equipment and robotics, and… Read More


Revolutionizing AI Infrastructure: Alchip and Ayar Labs’ Co-Packaged Optics Breakthrough at TSMC OIP 2025

Revolutionizing AI Infrastructure: Alchip and Ayar Labs’ Co-Packaged Optics Breakthrough at TSMC OIP 2025
by Daniel Nenni on 10-01-2025 at 6:00 am

Alchip TSMC OIP 2025

In the relentless race to power next-generation artificial intelligence (AI) systems, data connectivity has emerged as the critical bottleneck. As AI models balloon in size—from billions to trillions of parameters—compute resources alone are insufficient. According to Ayar Labs, approximately 70% of AI compute time is … Read More