How Samtec Helps Achieve 224G PAM4 in the Real World

How Samtec Helps Achieve 224G PAM4 in the Real World
by Mike Gianfagna on 05-15-2024 at 6:00 am

How Samtec Helps Achieve 224G PAM4 in the Real World

224 Gbps PAM4 gets attention for applications such as data center, AI/ML, accelerated computing, instrumentation and test and measurement. The question is how real is it and what are the challenges that need to be overcome to implement reliable channels at that data rate? If you wonder about these kinds of topics for your next design,… Read More


Siemens EDA Makes 3D IC Design More Accessible with Early Package Assembly Verification

Siemens EDA Makes 3D IC Design More Accessible with Early Package Assembly Verification
by Mike Gianfagna on 05-13-2024 at 6:00 am

Siemens EDA Makes 3D IC Design More Accessible with Early Package Assembly Verification

2.5D and 3D ICs present special challenges since these designs contain multiple chiplets of different materials integrated in all three dimensions. This complexity demands full assembly verification of the entire stack, considering all the subtle electrical and physical interactions of the complete system. Identifying… Read More


Webinar: Samtec and Achronix Expand AI in the Data Center

Webinar: Samtec and Achronix Expand AI in the Data Center
by Mike Gianfagna on 05-09-2024 at 10:00 am

Webinar Samtec and Achronix Expand AI in the Data Center

The performance demands of data centers continue to grow, driven to large degree by the ubiquitous use of complex AI algorithms. On April 25, Embedded Computing Design held an informative webinar on this topic. Two experts looked at the problem from the standpoint of processor architecture and communication strategies, which… Read More


Synopsys is Paving the Way for Success with 112G SerDes and Beyond

Synopsys is Paving the Way for Success with 112G SerDes and Beyond
by Mike Gianfagna on 05-08-2024 at 10:00 am

Synopsys is Paving the Way for Success with 112G SerDes and Beyond

Data communication speeds continue to grow. New encoding schemes, such as PAM-4 are helping achieve faster throughput. Compared to the traditional NRZ scheme, PAM4 can send twice the signal by using four levels vs. the two used in NRZ. The diagram at the top of this post shows the how data density is increased. With progress comes… Read More


Analog Bits Continues to Dominate Mixed Signal IP at the TSMC Technology Symposium

Analog Bits Continues to Dominate Mixed Signal IP at the TSMC Technology Symposium
by Mike Gianfagna on 05-06-2024 at 6:00 am

Analog Bits Continues to Dominate Mixed Signal IP at the TSMC Technology Symposium

The recent TSMC Technology Symposium in the Bay Area showcased the company’s leadership in areas such as solution platforms, advanced and specialty technologies, 3D enablement and manufacturing excellence. As always, the TSMC ecosystem was an important part of the story as well and that topic is the subject of this post. Analog… Read More


WEBINAR: Navigating the Power Challenges of Datacenter Infrastructure

WEBINAR: Navigating the Power Challenges of Datacenter Infrastructure
by Mike Gianfagna on 05-01-2024 at 10:00 am

WEBINAR Navigating the Power Challenges of Datacenter Infrastructure 1

 

We all know power and energy management is a top-of-mind item for many, if not all new system designs. Optimizing system power is a vexing problem. Success requires coordination of many hardware and software activities. The strategies to harmonize operation for high performance and low power are often not obvious. Much… Read More


Ceva Accelerates IoT and Smart Edge AI with a New Wireless Platform IP Family

Ceva Accelerates IoT and Smart Edge AI with a New Wireless Platform IP Family
by Mike Gianfagna on 04-29-2024 at 10:00 am

Ceva Accelerates IoT and Smart Edge AI with a New Wireless Platform IP Family

Ceva is a very focused company. In its words, the leader in innovative silicon and software IP solutions that enable smart edge products to connect, sense, and infer data more reliably and efficiently. You can see some of its accomplishments here. The company has been licensing IP for more than twenty years with more than 17 billion… Read More


Design Stage Verification Gives a Boost for IP Designers

Design Stage Verification Gives a Boost for IP Designers
by Mike Gianfagna on 04-25-2024 at 6:00 am

Design Stage Verification Gives a Boost for IP Designers

The concept of shift left is getting to be quite well-known. The strategy involves integrating various checks typically performed later in the design process into earlier stages. The main benefit is to catch and correct defects or errors at an earlier stage when it’s easier and faster to address. For complex SoC design, … Read More


How Secure-IC is Making the Cyber World a Safer Place

How Secure-IC is Making the Cyber World a Safer Place
by Mike Gianfagna on 04-23-2024 at 6:00 am

How Secure IC is Making the Cyber World a Safer Place

Securing the data and all the associated transactions that comprise our hyper-connected world is a daunting task. Security touches the hardware, software and all the channels connecting every device and every transaction. Threats can be embedded in software, hardware or systems can be compromised externally using a large … Read More


Soitec Delivers the Foundation for Next-Generation Interconnects

Soitec Delivers the Foundation for Next-Generation Interconnects
by Mike Gianfagna on 04-17-2024 at 6:00 am

Soitec Delivers the Foundation for Next Generation Interconnects

Soitec is a unique company that is at the center of major changes in our industry. Technology megatrends are fueling massive demand for semiconductors and this has increased the adoption of engineered substrates. As a global leader in the development of engineered substrates, Soitec is a company to watch. While this technology… Read More