There were many new agentic design flows introduced at DAC this year. Some from mainstream providers and others from new startups. The increased level of activity around this technology was good to see. Most of the approaches presented at the conference were targeting specific parts of the flow. Verification and debug were popular… Read More
Author: Mike Gianfagna
Agentrys Launches Agentic Design Automation at DAC 2026
DAC 2026: How Undo Makes AI for Chip Design Work Better
DAC was abuzz this year with new AI-fueled approaches to chip design and debug. New tools powered by deeply trained models opened substantial possibilities to deliver higher quality designs much faster, potentially with less resources. Every new technology has its risks. For AI-driven chip design some of those risks center … Read More
Mach42 Delivers a Different Take on AI in the Design Flow at DAC 2026
I believe DAC 2026 will be remembered as the turning point for AI assisted design. There has been discussion about AI infusion in EDA for a while now. Most of it was about how AI can be added to traditional tools to make existing methodologies better. This year, that changed. There were several new companies that highlighted a fundamentally… Read More
DAC 2026: Accellera Luncheon Panel on Embracing AI for Advanced Design and Verification
AI was a hot topic at DAC this year. If you attended the event, you’ve already heard about many new tools and systems that aim to improve time to market and quality for advanced semiconductors and systems. I had the pleasure of chairing an Accellera sponsored luncheon panel on Tuesday at DAC that took a different view of AI.
As AI and … Read More
DAC 2026: The Trouble with John Cooley’s Troublemaker Panel
For quite a few years, John Cooley has hosted the Troublemaker Panel at DAC. The event consists of a panel of senior executives from the EDA industry. John Cooley asks his readers for “edgy” questions to ask the panelists and on event day, he does just that. Those with complete responses that are backed with real data from real customers… Read More
Agentrys Designs a Real Chip with its Multi-Agent Workforce
The face of EDA is changing. For forty years, this industry has focused on optimizing algorithms for design, verification and implementation of chips. That work has delivered some ground-breaking innovations. Logic synthesis is a good example. There are so many more. Thanks to the innovations commonly referred to as Frontier… Read More
Must-See DAC Panel – Build vs Buy: Who Owns the Intelligence Behind Tomorrow’s Chips?
This year, DAC will be buzzing about AI from every direction. The debate of build vs. buy will also be a popular topic. And the debate of who owns the intellectual property embodied in chip designs and how to control it will also get a significant amount of airtime. These are all interesting and compelling discussion points. It turns… Read More
Agentrys Weighs in on LLM Benchmarking for Chip Design at DAC 2026
Si2 is conducting quite a few sessions at DAC this year covering everything from power model standards to agentic AI. There is one session that is a bit different, focusing on LLM benchmarking. Since AI is popping up everywhere, the ability to accurately assess and measure the quality of new models becomes more important. That’s… Read More
Webinar: Caspia Shows You How to Fix Security Flaws Before It’s Too Late
Chip-level vulnerability is becoming an existential threat for virtually all systems. The time to ensure your chip designs are resistant to these attacks is now. Caspia presented a webinar recently that provides important information on how to build attack-resistant chips. If you missed it, don’t worry. A replay link is coming.… Read More
Why Real-Time Intelligence is the Next Differentiator in Semiconductor Test
Even with advances in AI, automation, and advanced process technology, many semiconductor test operations still rely on reports generated hours after production has occurred. This creates a significant and growing problem. By the time engineers discover a yield excursion, parametric drift, tester issue, or an increase in… Read More
Claude as an EDA Tool Wiki