At Hot Chips 2026, OpenAI presented Jalapeño, an inference ASIC built with AI in the design loop. As reported from the session by ServeTheHome and Tom’s Hardware, OpenAI showed measured block-level wins over a human baseline — 56% on a BF16 multiply, alongside a 10% smaller matrix-unit area — within a roughly nine-month path from… Read More
Author: Mike Gianfagna
Moving Beyond AI-Assisted Design – Agentrys Shows the Way with Agentic Loop Engineering
A Migration Feasibility Study Can Turn an Uncertain Re-Design into a Measurable Engineering Project
Moving semiconductor IP to a new process technology is often treated as a redesign problem. For analog and mixed-signal designs, however, starting again from the schematic can overlook an asset: the engineering knowledge embedded in the existing physical layout.
Device sizing, matching, symmetry, routing, shielding, placement,… Read More
TSMC OIP Ecosystem Forum 2026: Spotlight on Emerging Technologies
The TSMC OIP Ecosystem Forum highlighted many accomplishments across TSMC’s vast ecosystem. Specific achievements with TSMC as well as collaborative work across several companies were all on display.
And there was an exhibit area where you could meet the companies behind many of these stories and learn more about them.
This … Read More
TSMC OIP Ecosystem Forum 2026: Broadcom’s View of ASICs and Ecosystems
I spent a significant part of my career in the ASIC business. This segment of semiconductors has always been challenging, difficult and invigorating. There is something special about delivering a working custom chip that enables your customer to bring a world-changing product to market. It has always been a highly competitive… Read More
TSMC OIP Ecosystem Forum 2026: Opening Remarks
The 2026 TSMC Open Innovation Platform (OIP) Ecosystem Forum was held on September 23, 2026, in Santa Clara, CA. This is the event where TSMC showcases the substantial progress made with its massive semiconductor ecosystem. As one would expect, AI was a key topic throughout the day, with some very impressive results reported and… Read More
Webinar – Avestra Explains How to Achieve Assertion Driven Silicon Success
Studies have shown that nearly 20% of the verification cycle is spent on assertion generation, debugging, and methodology integration. This work remains largely manual today or is delegated to general-purpose LLMs that can produce incorrect assertions more than 30% of the time. Avestra attacks this problem with agentic AI … Read More
Webinar – ChipAgents Shows You How to Break the Timing Closure Bottleneck with AI
We all know timing closure is one of the most challenging processes in chip design. Extracting actionable insight from massive timing reports, tracing violations back to RTL, and selecting the right fix across complex PPA tradeoffs all require deep expertise. And every change can trigger hours or days of tool runs and cross-team… Read More
DAC 2026: A Discussion of Who Owns the Intelligence Behind Tomorrow’s Chips and How to Make it Better
The industry is moving from simple documentation chatbots to agentic workflows capable of performing complex, multi-step tasks like design creation, verification, and library characterization. These agents are intended to enhance engineering productivity by roughly 50%. A panel of industry experts met at DAC to discuss… Read More
Follow the Money – Agentrys Raises $24.5 Million to Build Agentic Design Automation
Agentrys recently launched a new category of design technology, Agentic Design Automation (ADA). The approach promises to revolutionize AI deployment for chip design with technology that facilitates the building of targeted agentic design flows that get better with every run. There is a lot of information available on the … Read More
GenAlpha Brings a Practical Approach for Analog AI to DAC 2026
Agentic AI was everywhere at DAC 2026. Various focus areas were presented that covered many parts of the chip design flow. Verification and debug were a popular topic since so much time is spent there. Analog design is another pressure point. Every chip design has analog content. While the size of the analog blocks may not be huge,… Read More
SEMICON West’s Autonomous Fab Vision Needs a Decision-Escalation Design