Mach42 Delivers a Different Take on AI in the Design Flow at DAC 2026

Mach42 Delivers a Different Take on AI in the Design Flow at DAC 2026
by Mike Gianfagna on 08-06-2026 at 6:00 am

Mach42 Delivers a Different Take on AI in the Design Flow at DAC 2026

I believe DAC 2026 will be remembered as the turning point for AI assisted design. There has been discussion about AI infusion in EDA for a while now. Most of it was about how AI can be added to traditional tools to make existing methodologies better. This year, that changed. There were several new companies that highlighted a fundamentally… Read More


DAC 2026: Accellera Luncheon Panel on Embracing AI for Advanced Design and Verification

DAC 2026: Accellera Luncheon Panel on Embracing AI for Advanced Design and Verification
by Mike Gianfagna on 08-04-2026 at 2:00 pm

DAC 2026 Accellera Luncheon Panel on Embracing AI for Advanced Design and Verification

AI was a hot topic at DAC this year. If you attended the event, you’ve already heard about many new tools and systems that aim to improve time to market and quality for advanced semiconductors and systems. I had the pleasure of chairing an Accellera sponsored luncheon panel on Tuesday at DAC that took a different view of AI.

As AI and … Read More


DAC 2026: The Trouble with John Cooley’s Troublemaker Panel

DAC 2026: The Trouble with John Cooley’s Troublemaker Panel
by Mike Gianfagna on 07-31-2026 at 10:00 am

DAC 2026 The Trouble with John Cooley’s Troublemaker Panel

For quite a few years, John Cooley has hosted the Troublemaker Panel at DAC. The event consists of a panel of senior executives from the EDA industry. John Cooley asks his readers for “edgy” questions to ask the panelists and on event day, he does just that. Those with complete responses that are backed with real data from real customers… Read More


Agentrys Designs a Real Chip with its Multi-Agent Workforce

Agentrys Designs a Real Chip with its Multi-Agent Workforce
by Mike Gianfagna on 07-23-2026 at 2:00 pm

Agentrys Designs a Real Chip with its Multi Agent Workforce

The face of EDA is changing. For forty years, this industry has focused on optimizing algorithms for design, verification and implementation of chips. That work has delivered some ground-breaking innovations. Logic synthesis is a good example. There are so many more. Thanks to the innovations commonly referred to as FrontierRead More


Must-See DAC Panel – Build vs Buy: Who Owns the Intelligence Behind Tomorrow’s Chips?

Must-See DAC Panel – Build vs Buy: Who Owns the Intelligence Behind Tomorrow’s Chips?
by Mike Gianfagna on 07-23-2026 at 10:00 am

Panel

This year, DAC will be buzzing about AI from every direction. The debate of build vs. buy will also be a popular topic. And the debate of who owns the intellectual property embodied in chip designs and how to control it will also get a significant amount of airtime. These are all interesting and compelling discussion points. It turns… Read More


Agentrys Weighs in on LLM Benchmarking for Chip Design at DAC 2026

Agentrys Weighs in on LLM Benchmarking for Chip Design at DAC 2026
by Mike Gianfagna on 07-22-2026 at 2:00 pm

Agentrys Weighs in on LLM Benchmarking for Chip Design at DAC 2026

Si2 is conducting quite a few sessions at DAC this year covering everything from power model standards to agentic AI. There is one session that is a bit different, focusing on LLM benchmarking. Since AI is popping up everywhere, the ability to accurately assess and measure the quality of new models becomes more important. That’s… Read More


Webinar: Caspia Shows You How to Fix Security Flaws Before It’s Too Late

Webinar: Caspia Shows You How to Fix Security Flaws Before It’s Too Late
by Mike Gianfagna on 07-02-2026 at 10:00 am

Webinar Caspia Shows You How to Fix Security Flaws Before It’s Too Late FINAL V2

Chip-level vulnerability is becoming an existential threat for virtually all systems. The time to ensure your chip designs are resistant to these attacks is now. Caspia presented a webinar recently that provides important information on how to build attack-resistant chips. If you missed it, don’t worry. A replay link is coming.… Read More


Why Real-Time Intelligence is the Next Differentiator in Semiconductor Test

Why Real-Time Intelligence is the Next Differentiator in Semiconductor Test
by Mike Gianfagna on 07-02-2026 at 6:00 am

Why Real Time Intelligence is the Next Differentiator in Semiconductor Test

Even with advances in AI, automation, and advanced process technology, many semiconductor test operations still rely on reports generated hours after production has occurred. This creates a significant and growing problem. By the time engineers discover a yield excursion, parametric drift, tester issue, or an increase in… Read More


How to Free Yourself from Inconsistent Engineering Documentation Before It’s Too Late

How to Free Yourself from Inconsistent Engineering Documentation Before It’s Too Late
by Mike Gianfagna on 06-25-2026 at 10:00 am

How to Free Yourself from Inconsistent Engineering Documentation Before It’s Too Late

Embedded systems programs often fail because critical engineering documentation drifts out of alignment over time and distance. This results in a team that is correctly following the wrong instructions. All forms of engineering documentation suffer from this problem, and it really is the silent killer of many programs.

llmda.aiRead More


How Samtec Blazes a Trail to 224/448 Gbps at DesignCon 26

How Samtec Blazes a Trail to 224/448 Gbps at DesignCon 26
by Mike Gianfagna on 06-23-2026 at 6:00 am

How Samtec Blazes a Trail to 224:448 Gbps at DesignCon 26

I recently covered what Samtec was doing at DesignCon 26. Samtec has a tendency to dominate any show it attends in multiple dimensions. The prior post focused on the company’s contributions to the technical agenda and the high-profile experts in attendance. While all that is interesting and valuable, attending a large show like… Read More