TSMC OIP Ecosystem Forum 2026: Broadcom’s View of ASICs and Ecosystems

TSMC OIP Ecosystem Forum 2026: Broadcom’s View of ASICs and Ecosystems
by Mike Gianfagna on 09-30-2026 at 12:00 pm

TSMC OIP Ecosystem Forum 2026 Broadcom’s View of ASICs and Ecosystems

I spent a significant part of my career in the ASIC business. This segment of semiconductors has always been challenging, difficult and invigorating. There is something special about delivering a working custom chip that enables your customer to bring a world-changing product to market. It has always been a highly competitive… Read More


TSMC OIP Ecosystem Forum 2026: Opening Remarks

TSMC OIP Ecosystem Forum 2026: Opening Remarks
by Mike Gianfagna on 09-28-2026 at 12:00 pm

TSMC OIP Ecosystem Forum 2026 Opening Remarks

The 2026 TSMC Open Innovation Platform (OIP) Ecosystem Forum was held on September 23, 2026, in Santa Clara, CA. This is the event where TSMC showcases the substantial progress made with its massive semiconductor ecosystem. As one would expect, AI was a key topic throughout the day, with some very impressive results reported and… Read More


Webinar – Avestra Explains How to Achieve Assertion Driven Silicon Success

Webinar – Avestra Explains How to Achieve Assertion Driven Silicon Success
by Mike Gianfagna on 09-10-2026 at 2:00 pm

Webinar – Avestra Explains How to Achieve Assertion Driven Silicon Success

Studies have shown that nearly 20% of the verification cycle is spent on assertion generation, debugging, and methodology integration. This work remains largely manual today or is delegated to general-purpose LLMs that can produce incorrect assertions more than 30% of the time. Avestra attacks this problem with agentic AI … Read More


Webinar – ChipAgents Shows You How to Break the Timing Closure Bottleneck with AI

Webinar – ChipAgents Shows You How to Break the Timing Closure Bottleneck with AI
by Mike Gianfagna on 09-10-2026 at 6:00 am

Webinar – ChipAgents Shows You How to Break the Timing Closure Bottleneck with AI

We all know timing closure is one of the most challenging processes in chip design. Extracting actionable insight from massive timing reports, tracing violations back to RTL, and selecting the right fix across complex PPA tradeoffs all require deep expertise. And every change can trigger hours or days of tool runs and cross-team… Read More


DAC 2026: A Discussion of Who Owns the Intelligence Behind Tomorrow’s Chips and How to Make it Better

DAC 2026: A Discussion of Who Owns the Intelligence Behind Tomorrow’s Chips and How to Make it Better
by Mike Gianfagna on 09-02-2026 at 6:00 am

DAC 2026 A Discussion of Who Owns the Intelligence Behind Tomorrow’s Chips and How to Make it Better

The industry is moving from simple documentation chatbots to agentic workflows capable of performing complex, multi-step tasks like design creation, verification, and library characterization. These agents are intended to enhance engineering productivity by roughly 50%. A panel of industry experts met at DAC to discuss… Read More


Follow the Money – Agentrys Raises $24.5 Million to Build Agentic Design Automation

Follow the Money – Agentrys Raises $24.5 Million to Build Agentic Design Automation
by Mike Gianfagna on 09-01-2026 at 6:00 am

Follow the Money – Agentrys Raises $24.5 Million to Build Agentic Design Automation

Agentrys recently launched a new category of design technology, Agentic Design Automation (ADA). The approach promises to revolutionize AI deployment for chip design with technology that facilitates the building of targeted agentic design flows that get better with every run. There is a lot of information available on the … Read More


GenAlpha Brings a Practical Approach for Analog AI to DAC 2026

GenAlpha Brings a Practical Approach for Analog AI to DAC 2026
by Mike Gianfagna on 08-31-2026 at 10:00 am

GenAlpha Booth

Agentic AI was everywhere at DAC 2026. Various focus areas were presented that covered many parts of the chip design flow. Verification and debug were a popular topic since so much time is spent there. Analog design is another pressure point. Every chip design has analog content. While the size of the analog blocks may not be huge,… Read More


The End of “Good Enough” Timing Analysis

The End of “Good Enough” Timing Analysis
by Mike Gianfagna on 08-27-2026 at 6:00 am

The End of Good Enough Timing Analysis

Why Advanced-Node Clock Networks Need More Than Timing Closure

Timing closure has been one of the semiconductor industry’s most reliable measures of design readiness for decades. Static timing analysis (STA) is a critical enabler for this process. It allows analysis of enormous designs across millions of paths, multiple… Read More


Bronco AI at DAC 2026, What a Difference a Year Makes

Bronco AI at DAC 2026, What a Difference a Year Makes
by Mike Gianfagna on 08-26-2026 at 6:00 am

Bronco AI at DAC 2026, What a Difference a Year Makes

During my time at DAC 2026 I felt like I was attending two events. One was the traditional DAC where approaches to designing complex chips using the best tools and methodologies were the focus. There was another focus for the conference. This one was like the traditional DAC with an important difference. Here, the discussion centered… Read More


Agentrys Shows You How to Build a Multi-Agent System in 30 Minutes

Agentrys Shows You How to Build a Multi-Agent System in 30 Minutes
by Mike Gianfagna on 08-20-2026 at 2:00 pm

Agentrys Shows You How to Build a Multi Agent System in 30 Minutes

Agentrys believes that a purpose-built multi-agent system for chip design shouldn’t be a quarter-long project. Agentic AI systems are becoming quite popular to cut design time and increase quality for complex chip design projects. The challenge is finding the right agentic flow for a particular application. There are… Read More