As process nodes advance, circuit behavior becomes progressively more challenging to analyze and predict. Few systems reflect this challenge more clearly than the clock network. These large, complex networks no longer behave as ideal digital signals. Instead, they operate as distributed electrical systems shaped by non-linear… Read More
Author: Mike Gianfagna
Taming Advanced Node Clock Network Challenges: Duty Cycle
Siemens EDA Illuminates the Complexity of PCB Design
As heterogeneous multi-die design becomes more prevalent, the focus on advanced analysis has predictably shifted in that direction. While these challenges are important to overcome, we shouldn’t lose sight of how complete systems are built. Short and long reach communication channels, system-level power management and … Read More
Webinar: Why AI-Assisted Security Verification For Chip Design is So Important
It is well-known that AI is everywhere, and the incredible power of this new technology is enabled by highly complex, purpose-built silicon. But there is a silent enemy of this substantial, world-changing progress. Something that has the power to steal a bright future from all of us. The hardware root of trust for those advanced… Read More
How vHelm Delivers an Optimized Clock Network
In a prior post, I discussed how the clock is no longer just another signal at advanced nodes. Indeed, it is the most critical network on the chip. An optimized clock network can be the margin of victory for your next design. But extracting these benefits is challenging. The clock network is quite sensitive, and optimization can come… Read More
A Webinar About Electrical Verification – The Invisible Bottleneck in IC Design
Electrical rule checking (ERC) is a standard part of any design flow. There is a hidden problem with the traditional approach, however. As designs grow in complexity, whether full-custom analog, mixed-signal, or advanced-node digital, the limitations of traditional ERC tools are becoming more problematic. This can lead to… Read More
Superhuman AI for Design Verification, Delivered at Scale
There is a new breed of EDA emerging. Until recently, EDA tools were focused on building better chips, faster and with superior quality of results. Part of that process is verifying and debugging the resultant design. Thanks to ubiquitous AI workloads and multi-chip architectures, the data to be verified and debugged is exploding,… Read More
ClockEdge Delivers Precision, Visibility and Control for Advanced Node Clock Networks
At advanced nodes, the clock is no longer just another signal. It is the most critical and sensitive electrical network on the chip, and the difference between meeting performance targets and missing the tape-out often comes down to a few picoseconds, buried deep inside the clock distribution network. Yet many design teams still… Read More
A Tour of Advanced Data Conversion with Alphacore
There is always a lot of buzz about advanced AI workloads at trade shows. How to train them and how to run them. Advanced chip and multi-die designs are how AI is brought to life, so it was a perfect fit for discussion at a show. But there is another side of this discussion. Much of the work going on in AI workloads has to do with processing… Read More
I Have Seen the Future with ChipAgents Autonomous Root Cause Analysis
I have seen a lot of EDA tool demos in my time. More than I want to admit. The perceived quality of the demo usually came down to a combination of the speed of the tool, quality of results and the ease of navigating through the graphical user interface. For the last item, how easy the interface was on the eyes, how clear were the relationships… Read More
CDC Verification for Safety-Critical Designs – What You Need to Know
Verification is always a top priority for any chip project. Re-spins result in lost time-to-market and significant cost overruns. Chip bugs that make it to the field present another level of lost revenue, lost brand confidence and potential costly litigation. If the design is part of the avionics or control for an aircraft, the… Read More
AI Bubble?