Arteris Highlights a Path to Scalable Multi-Die Systems at the Chiplet Summit

Arteris Highlights a Path to Scalable Multi-Die Systems at the Chiplet Summit
by Mike Gianfagna on 03-23-2026 at 6:00 am

Arteris Highlights a Path to Scalable Multi Die Systems at the Chiplet Summit

At the recent Chiplet Summit, presentations, discussions and general participation could be broken down into a few broad categories. There were presentations of actual chiplet designs, either as building blocks or end products. There were presentations regarding design tools and methodologies to support and accelerate … Read More


Siemens Wins Best in Show Award at Chiplet Summit and Targets Broad 3D IC Design Enablement

Siemens Wins Best in Show Award at Chiplet Summit and Targets Broad 3D IC Design Enablement
by Mike Gianfagna on 03-19-2026 at 8:00 am

Siemens Wins Best in Show Award at Chiplet Summit and Targets Broad 3D IC Enablement

The recent Chiplet Summit in Santa Clara was buzzing with new designs and new design methods. It felt like the industry had turned a corner at this year’s event with lots of new technology and design success on display. Siemens EDA had a large presence at the show and took home the Best in Show Award for Packaging Design. There were a … Read More


Synopsys Explores AI/ML Impact on Mask Synthesis at SPIE 2026

Synopsys Explores AI/ML Impact on Mask Synthesis at SPIE 2026
by Mike Gianfagna on 03-16-2026 at 6:00 am

Synopsys Explores AI:ML Impact on Mask Synthesis at SPIE 2026

The SPIE Advanced Lithography + Patterning Symposium recently concluded. This is a popular event where leading researchers gather. Challenges such as optical and EUV lithography, patterning technologies, metrology, and process integration for semiconductor manufacturing and adjacent applications are all covered. This… Read More


Qnity and Silicon Catalyst Light a Path to Success at the Chiplet Summit

Qnity and Silicon Catalyst Light a Path to Success at the Chiplet Summit
by Mike Gianfagna on 03-11-2026 at 10:00 am

Qnity and Silicon Catalyst Light a Path to Success at the Chiplet Summit

The Chiplet Summit recently concluded. Multi-die heterogeneous design is a hot topic these days and chiplets are a key enabler for this trend. The conference was noticeably larger this year. There were many presentations and exhibits that focused on areas such as how to design chiplets, what standards are important, how to integrate… Read More


The Name Changes but the Vision Remains the Same – ESD Alliance Through the Years

The Name Changes but the Vision Remains the Same – ESD Alliance Through the Years
by Mike Gianfagna on 02-23-2026 at 6:00 am

The Name Changes but the Vision Remains the Same – ESD Alliance Through the Years

The Electronic System Design Alliance (ESDA) has been at the center of the EDA industry through its many changes over the years. It occurred to me that an update on this organization would be useful. ESDA is a technology community within SEMI and is managed primarily by a team of three who coordinate all its activities along with a … Read More


What is the 3nm Pessimism Wall and Why is it An Economic Crisis?

What is the 3nm Pessimism Wall and Why is it An Economic Crisis?
by Mike Gianfagna on 02-20-2026 at 8:00 am

What is the 3nm Pessimism Wall and Why is it An Economic Crisis?

Chip design is getting more difficult as technology advances. Everyone knows that. A lot of the discussion around these issues tends to focus on the demands posed by massive AI workloads and the challenges of shifting to heterogeneous multi-die design. While these create real problems, there is an underlying effect that is making… Read More


Samtec Ushers in a New Era of High-Speed Connectivity at DesignCon 2026

Samtec Ushers in a New Era of High-Speed Connectivity at DesignCon 2026
by Mike Gianfagna on 02-16-2026 at 10:00 am

Samtec Ushers in a New Era of High Speed Connectivity at DesignCon 2026

As I’ve discussed before, Samtec has a way of dominating every trade show the company participates in. The upcoming DesignCon event is no exception. At the show, Samtec will be discussing data rates up to 448 Gbps and signals up to 130 GHz. Beyond a rich set of demonstrations in the company’s booth, Samtec engineers will be participating… Read More


The Risk of Not Optimizing Clock Power

The Risk of Not Optimizing Clock Power
by Mike Gianfagna on 02-06-2026 at 6:00 am

The Risk of Not Optimizing Clock Power

Clock power is rarely the issue teams expect to limit advanced-node designs. Yet in many chips today, over-driven clock networks quietly consume disproportionate power, reduce thermal headroom, and can constrain achievable frequency. And all while passing traditional sign-off checks and often remaining locked in through… Read More


Taming Advanced Node Clock Network Challenges: Jitter

Taming Advanced Node Clock Network Challenges: Jitter
by Mike Gianfagna on 01-30-2026 at 6:00 am

Taming Advanced Node Clock Network Challenges Jitter

Clock jitter rarely fails in obvious ways. In advanced-node designs, its impact is often indirect, emerging through subtle timing uncertainty, interaction with power delivery noise, and compounding effects across large clock networks. These behaviors can quietly erode margin and predictability, even when conventional… Read More