For advanced semiconductor designs, achieving both design rule check clean layouts and optimal electrical performance is crucial for minimizing design iterations, reducing time-to-market and ensuring product reliability. Balancing electrical performance and layout integrity is a difficult task. Achieving an optimal… Read More
Author: Mike Gianfagna
Going Beyond DRC Clean with Calibre DE
How FD-SOI Powers the Future of AI in Automobiles
We are witnessing a significant revolution in automotive design. The software-defined vehicle is taking center stage as disruptive technologies are integrated into mass production. Areas such as autonomous driving, lighting, radar, and other camera-based sensors are all part of this revolution. AI is at the center of many… Read More
Is Arteris Poised to Enable Next Generation System Design?
The semiconductor ecosystem is changing. Monolithic design is becoming multi-die design. Processors no longer inform software development options. It’s now the other way around with complex AI software informing the design of purpose-built hardware. And all that special-purpose hardware needs drivers to make it come to … Read More
How Synopsys Enables Gen AI on the Edge
Artificial intelligence and machine learning have undergone incredible changes over the past decade or so. We’ve witnessed the rise of convolutional neural networks and recurrent neural networks. More recently, the rise of generative AI and transformers. At every step, accuracy has been improved as depicted in the graphic… Read More
Samtec Advances Multi-Channel SerDes Technology with Broadcom at DesignCon
There were many announcements and significant demonstrations of new technology at the recent DesignCon. The show celebrated its 30th anniversary this year and it has grown quite a bit. As in past years Samtec had a commanding presence at the show. There will be more about that in a moment, but first I want to focus on a substantial … Read More
Synopsys Expands Optical Interfaces at DesignCon
The exponential growth of cloud data centers is well-known. Driven by the demands of massive applications like generative AI, state-of-the-art data centers present substantial challenges in terms of power consumption. And AI is poised to drive a 160% increase in data center power demand while also increasing demands on storage… Read More
What is Different About Synopsys’ Comprehensive, Scalable Solution for Fast Heterogeneous Integration
Multi-die design has become the center of a lot of conversation lately. The ability to integrate multiple heterogeneous devices into a single package has changed the semiconductor landscape, permanently. This technology has opened a path for continued Moore’s Law scaling at the system level. What comes next will truly be exciting.… Read More
Webinar: Achieve Full Flow and Resource Management Visibility to Optimize Cost and Sustainability with Innova
The lifecycle for complex chip design includes many factors. Traditional systems focus on design tasks, associated schedules and manufacturing logistics. While these are important aspects of the project there is a lot more that can be measured, predicted and tracked. Taking a more holistic view of the project opens new opportunities… Read More
Synopsys Brings Embedded Memory to the Future with its Flexible, IP-Based Compilers
There is a revolution happening that is fueled by innovation in areas such as AI, IoT and autonomous driving. These new systems put incredible stress on next-generation semiconductor technology. Faster processing, higher density and lower latency must all be delivered with reduced power and thermal profiles. One technology… Read More
Intel Presents the Final Frontier of Transistor Architecture at IEDM
IEDM was buzzing with many presentations about the newest gate-all-around transistor. Both Intel and TSMC announced processes based on nanosheet technology. This significant process innovation allows the fabrication of silicon RibbonFET CMOS devices, which promise to open a new era of transistor scaling, keeping Moore’s… Read More
Rethinking Multipatterning for 2nm Node