Must-See DAC Panel – Build vs Buy: Who Owns the Intelligence Behind Tomorrow’s Chips?

Must-See DAC Panel – Build vs Buy: Who Owns the Intelligence Behind Tomorrow’s Chips?
by Mike Gianfagna on 07-23-2026 at 10:00 am

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This year, DAC will be buzzing about AI from every direction. The debate of build vs. buy will also be a popular topic. And the debate of who owns the intellectual property embodied in chip designs and how to control it will also get a significant amount of airtime. These are all interesting and compelling discussion points. It turns… Read More


Agentrys Weighs in on LLM Benchmarking for Chip Design at DAC 2026

Agentrys Weighs in on LLM Benchmarking for Chip Design at DAC 2026
by Mike Gianfagna on 07-22-2026 at 2:00 pm

Agentrys Weighs in on LLM Benchmarking for Chip Design at DAC 2026

Si2 is conducting quite a few sessions at DAC this year covering everything from power model standards to agentic AI. There is one session that is a bit different, focusing on LLM benchmarking. Since AI is popping up everywhere, the ability to accurately assess and measure the quality of new models becomes more important. That’s… Read More


Webinar: Caspia Shows You How to Fix Security Flaws Before It’s Too Late

Webinar: Caspia Shows You How to Fix Security Flaws Before It’s Too Late
by Mike Gianfagna on 07-02-2026 at 10:00 am

Webinar Caspia Shows You How to Fix Security Flaws Before It’s Too Late FINAL V2

Chip-level vulnerability is becoming an existential threat for virtually all systems. The time to ensure your chip designs are resistant to these attacks is now. Caspia presented a webinar recently that provides important information on how to build attack-resistant chips. If you missed it, don’t worry. A replay link is coming.… Read More


Why Real-Time Intelligence is the Next Differentiator in Semiconductor Test

Why Real-Time Intelligence is the Next Differentiator in Semiconductor Test
by Mike Gianfagna on 07-02-2026 at 6:00 am

Why Real Time Intelligence is the Next Differentiator in Semiconductor Test

Even with advances in AI, automation, and advanced process technology, many semiconductor test operations still rely on reports generated hours after production has occurred. This creates a significant and growing problem. By the time engineers discover a yield excursion, parametric drift, tester issue, or an increase in… Read More


How to Free Yourself from Inconsistent Engineering Documentation Before It’s Too Late

How to Free Yourself from Inconsistent Engineering Documentation Before It’s Too Late
by Mike Gianfagna on 06-25-2026 at 10:00 am

How to Free Yourself from Inconsistent Engineering Documentation Before It’s Too Late

Embedded systems programs often fail because critical engineering documentation drifts out of alignment over time and distance. This results in a team that is correctly following the wrong instructions. All forms of engineering documentation suffer from this problem, and it really is the silent killer of many programs.

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How Samtec Blazes a Trail to 224/448 Gbps at DesignCon 26

How Samtec Blazes a Trail to 224/448 Gbps at DesignCon 26
by Mike Gianfagna on 06-23-2026 at 6:00 am

How Samtec Blazes a Trail to 224:448 Gbps at DesignCon 26

I recently covered what Samtec was doing at DesignCon 26. Samtec has a tendency to dominate any show it attends in multiple dimensions. The prior post focused on the company’s contributions to the technical agenda and the high-profile experts in attendance. While all that is interesting and valuable, attending a large show like… Read More


WEBINAR: Engineering Documentation is a Critical Source of Truth – Do You Know if it’s Accurate?

WEBINAR: Engineering Documentation is a Critical Source of Truth – Do You Know if it’s Accurate?
by Mike Gianfagna on 06-11-2026 at 8:00 am

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Embedded systems programs rarely fail because of a lack of execution capability. They fail because critical engineering documentation drifts out of alignment over time and distance. Simply put, the team is correctly following the wrong instructions. This includes requirements, architecture, implementation, verification,… Read More


Learn How llmda Uses Agentic AI to Generate Hardware Docs & Keep Them Consistent

Learn How llmda Uses Agentic AI to Generate Hardware Docs & Keep Them Consistent
by Mike Gianfagna on 06-02-2026 at 8:00 am

If You Struggle with Up To Date Documentation llmda.ai Can Help

Accurate, complete, and consistent technical documentation is a critical element of success for any embedded system design project. This includes IP, SoCs, and the associated hardware and software infrastructure. When documentation contains errors, the consequences go beyond engineering inefficiency. Errors that drive… Read More


A Look at the High-Profile Speakers Presenting at #DAC2026

A Look at the High-Profile Speakers Presenting at #DAC2026
by Mike Gianfagna on 06-01-2026 at 10:00 am

A Look at the High Profile Speakers Presenting at #DAC2026

Many of us think of DAC as an important trade show for the Semiconductors and EDA industries. That is certainly part of the history of DAC, but the event is also a highly prestigious technical conference dating back to 1964. In fact, the exhibits at DAC began 20 years after the conference started. That long history as a premier technical… Read More


The Hidden Cost of Using Claude for Documentation

The Hidden Cost of Using Claude for Documentation
by Mike Gianfagna on 05-29-2026 at 8:00 am

Why Generic LLMs Fall Short for Critical Engineering Documentation

Engineering documentation has always been difficult to produce, maintain, and scale. But with the rise of generative AI, many organizations are asking a reasonable question: can a general-purpose large language model (LLM) like Claude automate the work? At first glance, the answer appears to be yes.

Modern LLMs can generate… Read More