DAC TechTalk – A Siemens and NVIDIA Perspective on Unlocking the Power of AI in EDA

DAC TechTalk – A Siemens and NVIDIA Perspective on Unlocking the Power of AI in EDA
by Mike Gianfagna on 08-05-2025 at 6:00 am

Screenshot

AI was everywhere at DAC. Presentations, panel discussions, research papers and poster sessions all had a strong dose of AI. At the DAC Pavillion on Monday two heavy weights in the industry, Siemens and NVIDIA took the stage to discuss AI for design, both present and future.  What made this event stand out for me was the substantial… Read More


Synopsys Webinar – Enabling Multi-Die Design with Intel

Synopsys Webinar – Enabling Multi-Die Design with Intel
by Mike Gianfagna on 08-04-2025 at 6:00 am

Synopsys Webinar – Enabling Multi Die Design with Intel

As we all know, the age of multi-die design has arrived. And along with it many new design challenges. There is a lot of material discussing the obstacles to achieve more mainstream access to this design architecture, and some good strategies to conquer those obstacles. Synopsys recently published a webinar that took this discussion… Read More


CAST Webinar About Supercharging Your Systems with Lossless Data Compression IPs

CAST Webinar About Supercharging Your Systems with Lossless Data Compression IPs
by Mike Gianfagna on 07-31-2025 at 10:00 am

CAST Webinar About Supercharging Your Systems with Lossless Data Compression IPs

Much of advanced technology is data-driven. From the cloud and AI accelerators to automotive processing and edge computing, data storage and transmission efficiency are of critical importance. It turns out that lossless data compression is a key ingredient to deliver these requirements.

While there are both software and hardware… Read More


Scaling 3D IC Technologies – Siemens Hosts a Meeting of the Minds at DAC

Scaling 3D IC Technologies – Siemens Hosts a Meeting of the Minds at DAC
by Mike Gianfagna on 07-24-2025 at 6:00 am

Scaling 3D IC Technologies – Siemens Hosts a Meeting of the Minds at DAC

3D IC was a very popular topic at DAC. The era of heterogeneous, multi-chip design is here.  There were a lot of research results and practical examples presented. What stood out for me was a panel at the end of day two of DAC that was hosted by Siemens. This panel brought together an impressive group of experts to weigh in on what was really… Read More


DAC News – proteanTecs Unlocks AI Hardware Growth with Runtime Monitoring

DAC News – proteanTecs Unlocks AI Hardware Growth with Runtime Monitoring
by Mike Gianfagna on 07-17-2025 at 6:00 am

DAC News – proteanTecs Unlocks AI Hardware Growth with Runtime Monitoring

As AI models grow exponentially, the infrastructure supporting them is struggling under the pressure. At DAC, one company stood out with a solution that doesn’t just monitor chips, it empowers them to adapt in real time to these new workload requirements.

Unlike traditional telemetry or post-silicon debug tools, proteanTecs… Read More


Perforce at DAC, Unifying Software and Silicon Across the Ecosystem

Perforce at DAC, Unifying Software and Silicon Across the Ecosystem
by Mike Gianfagna on 07-15-2025 at 6:00 am

Perforce at DAC, Unifying Software and Silicon Across the Ecosystem

As the new name reflects, chip and system design were a major focus at DAC. So was the role of AI to enable those activities. But getting an AI-enabled design flow to work effectively across chip, subsystem and system-level design presents many significant challenges. One important one is effectively managing the vast amount of… Read More


Arteris Simplifies Design Reuse with Magillem Packaging

Arteris Simplifies Design Reuse with Magillem Packaging
by Mike Gianfagna on 07-08-2025 at 6:00 am

Arteris Simplifies Design Reuse with Magillem Packaging

Many know Arteris as the “network-on-chip”, or NoC, company. Through acquisitions and forward-looking development, the footprint for Arteris has grown beyond smart interconnect IP. At DAC this year, Arteris highlighted its latest expansion with a new SoC integration automation product called Magillem Packaging. The announcement… Read More


Caspia Focuses Security Requirements at DAC

Caspia Focuses Security Requirements at DAC
by Mike Gianfagna on 07-07-2025 at 6:00 am

Caspia Highlights Security Requirements at DAC

As expected, security was a big topic at DAC this year. The growth of AI has demanded complex, purpose-built semiconductors to run ever-increasing workloads. AI has helped to design those complex chips more efficiently and with less power demands. There was a lot of discussion on these topics. But there is another part of this trend.… Read More


Webinar – Power is the New Performance: Scaling Power & Performance for Next Generation SoCs

Webinar – Power is the New Performance: Scaling Power & Performance for Next Generation SoCs
by Mike Gianfagna on 06-26-2025 at 10:00 am

Webinar Scaling Power Performance for Next Generation SoCs

What if you could reduce power and extend chip lifetime, without compromising performance? We all know the importance of power optimization for advanced SoCs. Thanks to the massive build out of AI workloads, power consumption has gone from a cost or cooling headache to an existential threat to the planet, if current power consumptions… Read More


Visualizing System Design with Samtec’s Picture Search

Visualizing System Design with Samtec’s Picture Search
by Mike Gianfagna on 06-25-2025 at 6:00 am

Visualizing System Design with Samtec’s Picture Search

If you’ve spent a lot of time in the chip or EDA business, “design” typically means chip design. These days it means heterogeneous multi-chip design. If you’ve spent time developing end products, “design” has a much broader meaning. Chips, subsystems, chassis and product packaging are in focus. This is just a short list if you consider… Read More