Can RISC-V Help Recast the DPU Race?

Can RISC-V Help Recast the DPU Race?
by Jonah McLeod on 08-26-2025 at 10:00 am

Can RISC V Help Qualcomm

ARM’s Quiet Coup in DPUs

The datacenter is usually framed as a contest between CPUs (x86, ARM, RISC-V) and GPUs (NVIDIA, AMD, custom ASICs). But beneath those high-profile battles, another silent revolution has played out: ARM quietly displaced Intel and AMD in the Data Processing Unit (DPU) market.

DPUs — also called SmartNICs… Read More


What XiangShan Got Right—And What It Didn’t Dare Try

What XiangShan Got Right—And What It Didn’t Dare Try
by Jonah McLeod on 08-12-2025 at 6:00 am

XiangShan

An Open ISA, a Closed Mindset — Predictive Execution Charts a New Path

The RISC-V revolution was never just about open instruction sets. It was a rare opportunity to break free from the legacy assumptions embedded in every generation of CPU design. For decades, architectural decisions have been constrained by proprietary patents,… Read More


Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot

Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot
by Jonah McLeod on 06-24-2025 at 10:00 am

Table 1

In 2003, legendary computer architect Michael J. Flynn issued a warning that most of the industry wasn’t ready to hear. The relentless march toward more complex CPUs—with speculative execution, deep pipelines, and bloated instruction handling—was becoming unsustainable. In a paper titled “Computer Architecture … Read More


Voice as a Feature: A Silent Revolution in AI-Enabled SoCs

Voice as a Feature: A Silent Revolution in AI-Enabled SoCs
by Jonah McLeod on 05-26-2025 at 10:00 am

Voice as a Feature

When Apple introduced Siri in 2011, it was the first serious attempt to make voice interaction a mainstream user interface. Embedded into the iPhone 4S, Siri brought voice into consumers’ lives not as a standalone product, but as a built-in feature—a hands-free way to interact with an existing device. Siri set the expectation… Read More


Feeding the Beast: The Real Cost of Speculative Execution in AI Data Centers

Feeding the Beast: The Real Cost of Speculative Execution in AI Data Centers
by Jonah McLeod on 04-30-2025 at 10:00 am

Per Module Cost Breakdown RISCV

For decades, speculative execution was a brilliant solution to a fundamental bottleneck: CPUs were fast, but memory access was slow. Rather than wait idly, processors guessed the next instruction or data fetch and executed it ‘just in case.’ Speculative execution traces its lineage back to Robert Tomasulo’s work… Read More


Predictive Load Handling: Solving a Quiet Bottleneck in Modern DSPs

Predictive Load Handling: Solving a Quiet Bottleneck in Modern DSPs
by Jonah McLeod on 04-17-2025 at 6:00 am

Predictive Load

When people talk about bottlenecks in digital signal processors (DSPs), they usually focus on compute throughput: how many MACs per second, how wide the vector unit is, how fast the clock runs. But ask any embedded AI engineer working on always-on voice, radar, or low-power vision—and they’ll tell you the truth: memory stalls … Read More


Even HBM Isn’t Fast Enough All the Time

Even HBM Isn’t Fast Enough All the Time
by Jonah McLeod on 04-07-2025 at 6:00 am

BW V Latency

Why Latency-Tolerant Architectures Matter in the Age of AI Supercomputing

High Bandwidth Memory (HBM) has become the defining enabler of modern AI accelerators. From NVIDIA’s GB200 Ultra to AMD’s MI400, every new AI chip boasts faster and larger stacks of HBM, pushing memory bandwidth into the terabytes-per-second range. … Read More


RISC-V’s Privileged Spec and Architectural Advances Achieve Security Parity with Proprietary ISAs

RISC-V’s Privileged Spec and Architectural Advances Achieve Security Parity with Proprietary ISAs
by Jonah McLeod on 03-12-2025 at 6:00 am

Security Article Intro ART

Because of its open and modular nature, RISC-V has faced recognizable security challenges stemming from fragmentation, performance inefficiencies, and inherent vulnerabilities. Fragmentation across implementations leads to inconsistencies, making it difficult to enforce uniform security measures. Performance… Read More


Harnessing Modular Vector Processing for Scalable, Power-Efficient AI Acceleration

Harnessing Modular Vector Processing for Scalable, Power-Efficient AI Acceleration
by Jonah McLeod on 02-24-2025 at 6:00 am

shutterstock 2425981653

The dominance of GPUs in AI workloads has long been driven by their ability to handle massive parallelism, but this advantage comes at the cost of high-power consumption and architectural rigidity. A new approach, leveraging a chiplet-based RISC-V vector processor, offers an alternative that balances performance, efficiency,… Read More


An Open-Source Approach to Developing a RISC-V Chip with XiangShan and Mulan PSL v2

An Open-Source Approach to Developing a RISC-V Chip with XiangShan and Mulan PSL v2
by Jonah McLeod on 02-13-2025 at 6:00 am

PastedGraphic 1

As RISC-V gains traction in the global semiconductor industry, developers are exploring fully open-source approaches to processor design. XiangShan, a high-performance RISC-V CPU project, combined with the Mulan Permissive License v2 (Mulan PSL v2), represents a community-driven, transparent alternative to proprietary… Read More