As IC designs become increasingly complex, traditional Design Rule Checking (DRC) methods are struggling to keep up. The old “construct by correction” approach, initially developed for simpler, custom layouts, is creating substantial runtime and resource bottlenecks. Traditional DRC relies on an iterative, sequential… Read More
Author: Daniel Payne
Getting Faster DRC Results with a New Approach
Automating Formal Verification
Formal verification methods are being adopted at a fast pace as a complement to traditional verification methods like functional simulation for IP blocks in SoC designs. I had a video meeting with Max Birtel, co-founder of LUBIS EDA and learned more about their history, products and vision. This company started recently in 2020… Read More
Heterogeneous 2D/3D Packaging Challenges
A growing trend in system design is the use of multiple ICs mounted in advanced packages, especially in high-performance computing and AI. These modern packages now integrate multiple ICs, often with high-bandwidth memory (HBM), resulting in hundreds of thousands of connections that need proper verification. Traditional… Read More
CES 2025 and all things Cycling
CES 2025 was held from January 7-10, once again in Las Vegas, so I attended virtually to gather together all of the tech and trends related to cycling, which is becoming more electrified each year. E-bikes return as the biggest category and from my cycling rides I can see how popular these bikes are becoming in Oregon for commuters … Read More
Reset Domain Crossing (RDC) Challenges
In the early days an IC had a single clock and a single reset signal, making it a simple matter to reset the chip into a known, stable state, so there was little need for detailed analysis. For modern designs there can be dozens to hundreds of clocks, creating separate domains and some use of asynchronous resets, so the challenge of ensuring… Read More
Electrical Rule Checking in PCB Tools
I’ve known about DRC (Design Rule Checking) for IC design, and the same approach can also be applied to PCB design. The continuous evolution of electronics has led to increasingly intricate PCB designs that require Electrical Rule Checking (ERC) to ensure that performance goals are met. This complexity poses several challenges… Read More
SystemC Update 2024
SystemC version 1.0 came out in 2000 as a C++ class library for system-level modeling and simulation, and on SemiWiki.com there are some 497 references to the language. I wanted to provide an update in this blog so that engineering teams can become more efficient in using SystemC on their SoC projects, saving time and improving product… Read More
WEBINAR: Elevate Your Analog Layout Design to New Heights
Analog IC layout is a demanding endeavor as it entails conforming to complex layout design rules, interpreting design intentions from the schematics and understanding arcane topics like transistor matching, noise tolerance, parasitics and latch up. These skills are often handed down from one generation to the next, one on … Read More
Handling Objections in UVM Code
You begin writing some UVM code and there are parts of the code that aren’t done yet, so you begin to use uvm_objection, guarding that code. Rich Edelman, a product engineer at Siemens doing verification debug and analysis, wrote a paper on this topic, which I just read. This blog covers the topic of objections and provides some different… Read More
Analog IC Migration using AI
My first job out of college was migrating a DRAM chip from one process node to a newer node, and it was a 100% manual process that required many months of effort. That need to migrate semiconductor IP to newer nodes is still with us today, and much automation has been applied to digital circuits, however migrating analog IP has proven… Read More
Rethinking Multipatterning for 2nm Node