GaN Device Design and Optimization with TCAD

GaN Device Design and Optimization with TCAD
by Daniel Payne on 10-07-2025 at 10:00 am

GaN Power, Frequency min

I’ve read articles about power electronics, RF systems and high-frequency applications using SiC and GaN transistors, especially in EVs and chargers, but hadn’t looked into the details of GaN devices. A recent Silvaco webinar proved to be just the format that I needed to learn more about GaN design and optimization. Udita Mittal,… Read More


Simulating Gate-All-Around (GAA) Devices at the Atomic Level

Simulating Gate-All-Around (GAA) Devices at the Atomic Level
by Daniel Payne on 09-17-2025 at 10:00 am

GAA FET min

Transistor fabrication has spanned the gamut from planar devices o FinFET to Gate-All-Around (GAA) as silicon dimensions have decreased in the quest for higher density, faster speeds and lower power. Process development engineers use powerful simulation tools to predict and even optimize transistor performance for GAA devices.… Read More


Something New in Analog Test Automation

Something New in Analog Test Automation
by Daniel Payne on 09-16-2025 at 10:00 am

IJTAG min

Digital design engineers have used DFT automation technologies like scan and ATPG for decades now, however, analog blocks embedded within SoCs have historically required that a test engineer write tests that require specialized expertise and that can take man-months to debug. Siemens has a long history in the DFT field, SPICE… Read More


Perforce and Siemens at #62DAC

Perforce and Siemens at #62DAC
by Daniel Payne on 08-28-2025 at 10:00 am

perforce siemens min

Wednesday was the last day at #62DAC for me and I attended an Exhibitor Session entitled, Engineering the Semiconductor Digital Thread, which featured Vishal Moondhra, VP Solutions Engineering of Perforce IPLM and Michael Munsey, VP Semiconductor Industry at Siemens Digital Industries. Instead of just talking from slides,… Read More


Moving Beyond RTL at #62DAC

Moving Beyond RTL at #62DAC
by Daniel Payne on 08-14-2025 at 10:00 am

beyond rtl min

Hardware designers have been using RTL and hardware description languages since the 1980s, yet many attempts at moving beyond RTL have tried to gain a foothold. At the #62DAC event I spent some time with Mike Fingeroff, the Chief High-Level Synthesis Technologist to understand what his company Rise Design Automation is up to. … Read More


Chiplets and Cadence at #62DAC

Chiplets and Cadence at #62DAC
by Daniel Payne on 08-12-2025 at 10:00 am

SoC Cockpit Concept min

Using chiplets is an emerging trend well-covered at #62DAC and they even had a dedicated Chiplet Pavilion, so I checked out the presentation from Dan Slocombe, Design Engineering Architect in the Compute Solutions Group at Cadence. In a short 20 minutes Dan managed to cover a lot of ground, so this blog will summarize the key  points.… Read More


Software-defined Systems at #62DAC

Software-defined Systems at #62DAC
by Daniel Payne on 08-06-2025 at 10:00 am

siemens panel on software-defined systems min

Modern EVs are prime examples of software-defined systems, so I attended a #62DAC panel session hosted by Siemens to learn more from experts at Collins Aerospace, Arm, AMD and Siemens. Here’s the list of panelists that span several domains, and what follows is my paraphrase of the discussion topics.

Panel Discussion

Q: How does… Read More


Digital Implementation and AI at #62DAC

Digital Implementation and AI at #62DAC
by Daniel Payne on 08-04-2025 at 10:00 am

aprisa at #62dac

My first panel discussion at DAC 2025 was all about using AI for digital implementation, as Siemens has a digital implementation tool called Aprisa  which has been augmented with AI to produce better results, faster. Panelists were from Samsung, Broadcom, MaxLinear, AWS and Siemens. In the past it could take an SoC design team… Read More


Calibre Vision AI at #62DAC

Calibre Vision AI at #62DAC
by Daniel Payne on 07-29-2025 at 10:00 am

calibre vision ai min

Calibre is a well-known EDA tool from Siemens that is used for physical verification, but I didn’t really know how AI technology was being used, so I attended a Tuesday session at #62DAC to get up to speed. Priyank Jain, Calibre Product Management presented slides and finished up with a Q&A session.

In the semiconductor world… Read More


Analysis and Exploration of Parasitic Effects

Analysis and Exploration of Parasitic Effects
by Daniel Payne on 07-23-2025 at 10:00 am

parasitc elements min

With advanced semiconductor processes continuing to shrink, the number and complexity of parasitic elements in designs grows exponentially contributing to one of the most significant bottlenecks in the design flow. Undetected parasitic-induced issues can be extremely costly, often resulting in tape-out delays.

Silvaco… Read More