Custom IC design has demanding technical requirements to produce accurate simulation results for timing and power analysis in the shortest run times. EDA vendors have been rushing to use AI and ML technology to meet these analysis requirements. I attended a webinar from Siemens on accelerating iterative design cycles with Solido… Read More
Author: Daniel Payne
Custom IC Design using Additive Learning
Smarter IC Layout Parasitic Analysis
IC layout parasitics dominate the performance of custom digital, analog and mixed-signal designs, so the challenge becomes how to identify the root causes and to quantify the effects of parasitics during early design stages. The old method of iterating between layout, extraction, SPICE simulation, followed by manual debug… Read More
Advances in ATPG from Synopsys
I first learned about ATPG – Automatic Test Program Generation in the 1980s at Silicon Compilers, then continued in the 90s at Viewlogic with the Sunrise tools, so it was illuminating to get an update from Synopsys on their ATPG technology by attending a webinar. Synopsys over the years has developed a family of test tools, shown … Read More
CES 2026 and all things Cycling
I just completed the annual Rapha 500 Challenge on Strava by cycling 869 km in eight days, so it’s time to give you my annual recap of CES 2026 and all things cycling. Similar to previous years the big push again in 2026 are e-bikes and even e-motos. The AI acronym was everywhere too in product names and announcements as physical… Read More
Signal Integrity Verification Using SPICE and IBIS-AMI
High-speed signals enable electronic systems by using memory interfaces, SerDes channels, data center backplanes and connectivity in automobiles. Challenges arise from signal distortions like inter-symbol interference, channel loss and dispersion effects. Multi-gigabit data transfer rates in High-Bandwidth Memory… Read More
What’s New with IP Lifecycle Management (IPLM)
I’ve blogged about Methodics before they were acquired by Perforce back in 2020, so I wanted to get an update on Perforce IPLM (IP Lifecycle Management) by attending their recent webinar. Hassan Ali Shah, Senior Product Manager and Rien Gahlsdor, Perforce IPLM Product Owner were the two webinar presenters. Their IPLM enables … Read More
Transforming Functional Verification through Intelligence
SoC projects are running behind schedule as design and verification complexity has increased dramatically, so just adding more engineers, more tests and more compute aren’t the answer. The time is ripe to consider smarter ways to improve verification efficiency. The added complexity of multiple embedded processors, multiple… Read More
Boosting SoC Design Productivity with IP-XACT
IP-XACT, defined by IEEE 1685, is a standard that pulls together IP packaging, integration, and reuse. For anyone building modern SoCs (Systems on Chip), IP-XACT isn’t just another XML schema: it is a productivity multiplier and a risk-reduction tool that brings order to your electronic system design.
What is IP-XACT?
IP-XACT… Read More
TCAD Update from Synopsys
We live in an exploding AI world, and this has put pressure on foundries to deliver new products faster than ever before. Any help to accelerate the semiconductor R&D goes a long way to make the life of Fab engineers easier. EDA tools in the TCAD (Technology Computer Aided Design) category are critical for TCAD engineers to accelerating… Read More
Assertion IP (AIP) for Improved Design Verification
Over the years design reuse methodology created a market for Semiconductor IP (SIP), now with formal techniques there’s a need for Assertion IP (AIP). Where each AIP is a reusable and configurable verification component used in hardware design to detect protocol and functional violations in a Design Under Test (DUT). LUBIS … Read More
TSMC Process Simplification for Advanced Nodes