Lowering the DFT Cost for Large SoCs with a Novel Test Point Exploration & Implementation Methodology

Lowering the DFT Cost for Large SoCs with a Novel Test Point Exploration & Implementation Methodology
by Daniel Nenni on 10-03-2023 at 6:00 am

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With the increasing on-chip integration capabilities, large scale electronic systems can be integrated into a single System-on-Chip or SoC. New manufacturing test challenges are raised for more advanced technology nodes where both quality and cost during testing are affected. A typical parameter is test coverage which impacts… Read More


The True Power of the TSMC Ecosystem!

The True Power of the TSMC Ecosystem!
by Daniel Nenni on 10-02-2023 at 6:00 am

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The 15th TSMC Open Innovation Platform® (OIP) was held last week. In preparation we did a podcast with one of the original members of the TSMC OIP team Dan Kochpatcharin. Dan and I talked about the early days before OIP when we did reference flows together. Around 20 years ago I did a career pivot and focused on Strategic Foundry Relationships.… Read More


CEO Interview: Stephen Rothrock of ATREG

CEO Interview: Stephen Rothrock of ATREG
by Daniel Nenni on 09-29-2023 at 6:00 am

Stephen Rothrock ATREG

Stephen Rothrock founded ATREG in 2000 to help global advanced technology companies divest and acquire infrastructure-rich manufacturing assets. Over the last 25 years, his firm has completed more than 100 transactions, representing over 40% of all global operational wafer fab sales in the semiconductor industry for operational,… Read More


WEBINAR: Emulation and Prototyping in the age of AI

WEBINAR: Emulation and Prototyping in the age of AI
by Daniel Nenni on 09-27-2023 at 8:00 am

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Artificial Intelligence is now the primary driver of leading edge semiconductor technology and that means performance is at a premium and time to market will be measured in billions of dollars of revenue. Emulation and Prototyping have never been more important and we are seeing some amazing technology breakthroughs including… Read More


Power Supply Induced Jitter on Clocks: Risks, Mitigation, and the Importance of Accurate Verification

Power Supply Induced Jitter on Clocks: Risks, Mitigation, and the Importance of Accurate Verification
by Daniel Nenni on 09-27-2023 at 6:00 am

Jitter Analysis

In the realm of digital systems, clocks play a crucial role in synchronizing various components and ensuring smooth flow of logic propagation. However, the accuracy of clocks can be significantly affected by power supply induced jitter. Jitter refers to the deviation in the timing of clock signals with PDN noise compared to ideal… Read More


WEBINAR: Why Rigorous Testing is So Important for PCI Express 6.0

WEBINAR: Why Rigorous Testing is So Important for PCI Express 6.0
by Daniel Nenni on 09-25-2023 at 8:00 am

PCIe IO bandwidth doubles every 3 years

In the age of rapid technological innovation, hyperscale datacenters are evolving at a breakneck pace. With the continued advancements in CPUs, GPUs, accelerators, and switches, faster data transfers are now paramount. At the forefront of this advancement is PCI Express (PCIe®), which has become the de-facto standard of interconnect… Read More


TSMC’s First US Fab

TSMC’s First US Fab
by Daniel Nenni on 09-25-2023 at 6:00 am

WaferTech TSMC

TSMC originally brought the pure-play foundry business to the United States in 1996 through a joint venture with customers Altera, Analog Devices, ISSI, and private investors (no government money). Altera is now part of Intel but ADI is still a top TSMC customer and enthusiastic supporter. I have seen the ADI CEO Vincent Roche … Read More


CEO Interview: Dr. Tung-chieh Chen of Maxeda

CEO Interview: Dr. Tung-chieh Chen of Maxeda
by Daniel Nenni on 09-22-2023 at 6:00 am

Dr. Tung chieh Chen of Maxeda

Dr. Tung-chieh Chen has been serving as the CEO of Maxeda Technology since 2015. In 2021, at DAC, the largest EDA conference, Dr. Chen was honored with the Under-40 Innovators Award in recognition of his exceptional achievements and contributions to EDA development. He is the infrastructure designer of NTUplace, a circuit placer… Read More


The TSMC OIP Backstory

The TSMC OIP Backstory
by Daniel Nenni on 09-18-2023 at 6:00 am

TSMC OIP 2023

This is the 15th anniversary of the TSMC Open Innovation Platform (OIP). The OIP Ecosystem Forum will kick off on September 27th in Santa Clara, California and continue around the world for the next two months in person and on-line in North America, Europe, China, Japan, Taiwan, and Israel. These are THE most attended semiconductor… Read More


CEO Interview: Koen Verhaege, CEO of Sofics

CEO Interview: Koen Verhaege, CEO of Sofics
by Daniel Nenni on 09-15-2023 at 6:00 am

CEO Interview Koen Verhaege, CEO of Sofics

Koen Verhaege, CEO of Sofics (“Solutions for ICs”), has developed his career first as an engineer, later as a business leader and entrepreneur, working on IP development and valorisation. Koen’s technical accomplishments, publications and patents are in the field of on-chip ESD protection design.

Today, Koen… Read More