Sigasi at the 2024 Design Automation Conference

Sigasi at the 2024 Design Automation Conference
by Daniel Nenni on 06-20-2024 at 2:00 pm

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Sigasi® will demonstrate its Sigasi Visual HDL™ (SVH™) portfolio during DAC, showing how it supports the shift-left methodology for chip design, catching specification errors early in the design cycle and fixing the inefficient HDL-based design flow.

The traditional HDL workflow cannot accommodate the massive amounts of… Read More


Arteris at the 2024 Design Automation Conference

Arteris at the 2024 Design Automation Conference
by Daniel Nenni on 06-17-2024 at 2:00 pm

DAC 2024 Banner

Arteris, a leading provider of system IP, will exhibit at DAC 2024, June 23-27, booth #1506. The company will demonstrate its latest technology including network-on-chip interconnect IP and SoC integration automation solutions. The products highlighted include CSRCompiler, Ncore Cache Coherent NoC IP and FlexNoC 5 interconnect… Read More


Something new in High Level Synthesis and High Level Verification

Something new in High Level Synthesis and High Level Verification
by Daniel Payne on 06-11-2024 at 10:00 am

catapult covercheck min

As SoC complexities continue to expand to billions of transistors, the quest for higher levels of design automation also rises. This has led to the adoption of High-Level Synthesis (HLS), using design languages such as C++ and SystemC, which is more productive than traditional RTL design entry methods. In the RTL approach there… Read More


WEBINAR: Redefining Security – The challenges of implementing Post-Quantum Cryptography (PQC)

WEBINAR: Redefining Security – The challenges of implementing Post-Quantum Cryptography (PQC)
by Daniel Nenni on 06-11-2024 at 8:00 am

Secure IC SemiWiki

In the late 1970s, cryptographic history saw the emergence of two seminal algorithms: McEliece and RSA. At that time, quantum threats were theoretical, and the selection criteria for cryptographic algorithms prioritized public key length and execution time, leading to RSA’s prominence while McEliece remained obscure… Read More


Webinar – CHERI: Fine-Grained Memory Protection to Prevent Cyber Attacks

Webinar – CHERI: Fine-Grained Memory Protection to Prevent Cyber Attacks
by Mike Gianfagna on 05-27-2024 at 6:00 am

Webinar – CHERI Fine Grained Memory Protection to Prevent Cyber Attacks

Cyber attacks are top of mind for just about everyone these days. As massive AI data sets become more prevalent (and more valuable), data security is no longer “nice to have”. Rather, it becomes critical for continued online operation and success. The AI discussion is a double-edged sword as well. While AI enables many new and life-changing… Read More


Sondrel’s Drive in the Automotive Industry

Sondrel’s Drive in the Automotive Industry
by Daniel Nenni on 05-16-2024 at 10:00 am

Oliver Jones VP Worldwide Sales and Marketing at Sondrel

Ollie Jones, Vice President of Strategic Sales at Sondrel, has worked extensively across Europe, North America and Asia and has held a variety of commercial leadership roles in FTSE 100, private equity owned and start-up companies.

Most recently Ollie was Chief Commercial Officer for an EV battery start up where he led the acquisition… Read More


ARC-V portfolio plus mature software IP targets three tiers

ARC-V portfolio plus mature software IP targets three tiers
by Don Dingee on 05-13-2024 at 10:00 am

ARC-V portfolio from Synopsys

Synopsys is bridging its long-running ARC® processor IP strategy into a RISC-V architecture – Bernard Murphy introduced the news here on SemiWiki last November. We’re getting new insight from Synopsys on its ARC-V portfolio and how they see RISC-V IP plus their mature software development toolchain IP fitting customer needs… Read More


Fault Simulation for AI Safety. Innovation in Verification

Fault Simulation for AI Safety. Innovation in Verification
by Bernard Murphy on 03-27-2024 at 6:00 am

Innovation New

More automotive content 😀

In modern cars, safety is governed as much by AI-based functions as by traditional logic and software. How can these functions be fault-graded for FMEDA analysis? Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO)… Read More


Andes Technology: Pioneering the Future of RISC-V CPU IP

Andes Technology: Pioneering the Future of RISC-V CPU IP
by Frankwell Lin on 03-25-2024 at 6:00 am

Table 1

On September 13, 2021, Andes Technology Corporation successfully issued its GDR (Global Depositary Receipt) public offering on the Luxembourg Stock Exchange. At the time it made Andes the only international public RISC-V Instruction set architecture (ISA) CPU IP supplier. This allowed investors around the world to participate… Read More


2024 Outlook with Hassan Triqui CEO of Secure-IC

2024 Outlook with Hassan Triqui CEO of Secure-IC
by Daniel Nenni on 03-11-2024 at 10:00 am

Hassan Triqui

Hassan TRIQUI has over 20 years of experience in the technology sector. Prior to spearheading Secure-IC’s development into a major player in embedded cybersecurity solutions, Hassan was a former senior executive at Thales and Thomson. Hassan is a pioneer, a Brittany Tech patriot, and passionate about providing solutions that… Read More