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Sr. FPGA Engineer

Sr. FPGA Engineer
by Admin on 08-17-2022 at 2:41 pm

Website Achronix

Job Description/Responsibilities

The successful candidate will be responsible for the functional verification of high-performance digital logic of the core fabric for standalone and embedded FPGAs.

Responsibilities include the following:

  • Write constrained-random and directed test cases in Verilog/SystemVerilog to verify core fabric functionality
  • Run functional simulations and regressions, including gate level and timing annotated simulations
  • Debug issues, report and track bugs to closure
  • Collect coverage metrics and track verification progress
  • Optimize existing test suites based on various constraints (memory usage, test time, etc.)
  • Support porting of the verification infrastructure for post-silicon validation
  • Mentor junior engineers

Required Skills and Qualifications

  • Experience with Simulation, Debugging and Formal Verification
  • Experience in Verilog coding and debugging
  • Proficiency in using a scripting language (e.g., Python, Perl)
  • Experience designing/maintaining flows and methodologies from scratch, especially across multiple teams
  • Well organized and strong communication skills
  • Experience with UVM or SystemVerilog for verification is a plus
  • Familiarity with using and/or designing for FPGAs is a plus
  • Familiarity with revision-control systems (e.g., perforce, git) is a plus


  • BS/MS in Computer Engineering or Computer Science (or related) + 2–6 years’ experience
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