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Why chip design needs industrial-grade EDA AI

Why chip design needs industrial-grade EDA AI
by Admin on 11-25-2025 at 10:00 am

EDA AI consumer vs industrial 72dpi

By Niranjan Sitapure

Artificial intelligence (AI) is reshaping industries worldwide. Consumer-grade AI solutions are getting significant attention in the media for their creativity, speed, and accessibility—from ChatGPT and Meta’s AI app to Gemini for image creation, Sora for video, Sona for music, and Perplexity for web… Read More


Mixel Company Update 2025

Mixel Company Update 2025
by Daniel Nenni on 11-25-2025 at 6:00 am

Mixel Update 2025 SemiWiki

Mixel, Inc., a longtime leader in mixed-signal and MIPI® interface IP, entered a new chapter in its history following its acquisition by Silvaco Group, Inc., a global provider of design software and semiconductor IP. The acquisition, completed earlier in 2025, marks a strategic move that combines Silvaco’s deep expertise in… Read More


Cloud-Accelerated EDA Development

Cloud-Accelerated EDA Development
by Admin on 11-24-2025 at 10:00 am

Figure 4

By Nikhil Sharma, Sunghwan Son, Paul Mantey

The semiconductor industry faces an unprecedented crisis that threatens the very foundation of technological innovation. According to the latest Siemens EDA / Wilson Research Study, first-silicon success rates have plummeted to just 14%[1]—the lowest figure in more than twenty… Read More


A Tour of Advanced Data Conversion with Alphacore

A Tour of Advanced Data Conversion with Alphacore
by Mike Gianfagna on 11-24-2025 at 6:00 am

A Tour of Advanced Data Conversion with Alphacore

There is always a lot of buzz about advanced AI workloads at trade shows. How to train them and how to run them. Advanced chip and multi-die designs are how AI is brought to life, so it was a perfect fit for discussion at a show. But there is another side of this discussion. Much of the work going on in AI workloads has to do with processing… Read More


Self-Aligned Spacer Patterning for Minimum Pitch Metal in DRAM

Self-Aligned Spacer Patterning for Minimum Pitch Metal in DRAM
by Fred Chen on 11-23-2025 at 10:00 am

Spacer Patterning for Minimum Pitch Metal in DRAM 1

The patterning of features outside a DRAM cell array can be just as challenging as those within the array itself [1]. The array contains features which are densely packed, but regularly arranged. On the other hand, outside the array, the minimum pitch features, such as the lowest metal lines in the periphery for the sense amplifier… Read More


CEO Interview with Dr. Peng Zou of PowerLattice

CEO Interview with Dr. Peng Zou of PowerLattice
by Daniel Nenni on 11-23-2025 at 8:00 am

Dr. Peng Zou President & CEO, Co Founder

Dr. Zou is one of the industry’s leading experts in power delivery for high performance processors.  Before founding PowerLattice, he held technical leadership roles at Qualcomm/NUVIA, Huawei and Intel, where he led the multidisciplinary teams advancing integrated voltage regulator technologies across magnetic materials,… Read More


Video EP12: How Mach42 is Changing Analog Verification with Antun Domic

Video EP12: How Mach42 is Changing Analog Verification with Antun Domic
by Daniel Nenni on 11-21-2025 at 10:00 am

In this episode of the Semiconductor Insiders video series, Dan is joined by Antun Domic, who discusses Mach42’s work on AI and analog verification. Antun covers many aspects of analog/AMS verification and how Mach42’s unique AI-fueled approach provides significant benefits. He explains the balance of speed … Read More


Silicon Creations Company Update 2025

Silicon Creations Company Update 2025
by Daniel Nenni on 11-21-2025 at 6:00 am

Silicon Creations PLL

Silicon Creations continues to strengthen its position as one of the most reliable and widely used analog and mixed-signal IP providers in the semiconductor industry. Founded in 2006, the company focuses on high-performance and low-risk IP solutions including PLLs, oscillators, SerDes interfaces, and high-speed differential

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Live Webinar: Considerations When Architecting Your Next SoC: NoC with Arteris and Aion Silicon

Live Webinar: Considerations When Architecting Your Next SoC: NoC with Arteris and Aion Silicon
by Daniel Nenni on 11-20-2025 at 10:00 am

square 3 (1)

The explosive growth of AI and accelerated computing is placing unprecedented demands on system-on-chip (SoC) design. Modern AI workloads require extremely high bandwidth, ultra-low latency, and energy-efficient data movement across increasingly heterogeneous architectures. As SoCs scale to incorporate clusters of… Read More


WEBINAR: Is Agentic AI the Future of EDA?

WEBINAR: Is Agentic AI the Future of EDA?
by Admin on 11-20-2025 at 6:00 am

NetApp Cadence Webinar Banner

The semiconductor industry is entering a transformative era, and few trends are generating more discussion or confusion than Agentic AI. From autonomous design exploration to next-generation verification strategies, Agentic AI promises dramatic changes in how chips are conceived, validated, and delivered. But as with … Read More